diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 3350e04ab..622de490e 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -678,7 +678,7 @@ int armv7m_checksum_memory(struct target *target,
 	if (retval == ERROR_OK)
 		*checksum = buf_get_u32(reg_params[0].value, 0, 32);
 	else
-		LOG_ERROR("error executing cortex_m3 crc algorithm");
+		LOG_ERROR("error executing cortex_m crc algorithm");
 
 	destroy_reg_param(&reg_params[0]);
 	destroy_reg_param(&reg_params[1]);
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index a7cf18f75..1d08c95fc 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2192,7 +2192,7 @@ COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
 	}
 
 	n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m3->isrmasking_mode);
-	command_print(CMD_CTX, "cortex_m3 interrupt mask %s", n->name);
+	command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name);
 
 	return ERROR_OK;
 }
@@ -2229,7 +2229,7 @@ COMMAND_HANDLER(handle_cortex_m3_reset_config_command)
 			break;
 	}
 
-	command_print(CMD_CTX, "cortex_m3 reset_config %s", reset_config);
+	command_print(CMD_CTX, "cortex_m reset_config %s", reset_config);
 
 	return ERROR_OK;
 }
@@ -2239,7 +2239,7 @@ static const struct command_registration cortex_m3_exec_command_handlers[] = {
 		.name = "maskisr",
 		.handler = handle_cortex_m3_mask_interrupts_command,
 		.mode = COMMAND_EXEC,
-		.help = "mask cortex_m3 interrupts",
+		.help = "mask cortex_m interrupts",
 		.usage = "['auto'|'on'|'off']",
 	},
 	{