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rtos: Fix XPSR_OFFSET for cortex_m4f stacking 

Structures rtos_standard_Cortex_M4F_stacking and 
rtos_standard_Cortex_M4F_FPU_stacking in rtos_standard_stackings.c 
where using rtos_standard_Cortex_M3_stack_align for the stack-align 
function. This function calls rtos_Cortex_M_stack_align with 
XPSR_OFFSET = 0x3c. This offset is correct for cortex-M3 but not for 
cortex-M4F and cortex-M4F with fpu. This patch adds stack_align 
functions for M4F an M4F_FPU

Change-Id: If6a90b1898fccbb85619a10f3aef5277dd88ce47
Signed-off-by: Armin van der Togt <armin@otheruse.nl>
Reviewed-on: http://openocd.zylin.com/4037
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Armin van der Togt 2017-03-02 10:39:26 +01:00 committed by Matthias Welwarsky
parent db456e209f
commit 4f2c3e6c4f
1 changed files with 21 additions and 2 deletions
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23
src/rtos/rtos_standard_stackings.c
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@ -229,6 +229,25 @@ static int64_t rtos_standard_Cortex_M3_stack_align(struct target *target,
stack_ptr, XPSR_OFFSET); stack_ptr, XPSR_OFFSET);
} }
static int64_t rtos_standard_Cortex_M4F_stack_align(struct target *target,
const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
int64_t stack_ptr)
{
const int XPSR_OFFSET = 0x40;
return rtos_Cortex_M_stack_align(target, stack_data, stacking,
stack_ptr, XPSR_OFFSET);
}
static int64_t rtos_standard_Cortex_M4F_FPU_stack_align(struct target *target,
const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
int64_t stack_ptr)
{
const int XPSR_OFFSET = 0x80;
return rtos_Cortex_M_stack_align(target, stack_data, stacking,
stack_ptr, XPSR_OFFSET);
}
const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = { const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = {
0x40, /* stack_registers_size */ 0x40, /* stack_registers_size */
-1, /* stack_growth_direction */ -1, /* stack_growth_direction */
@ -241,7 +260,7 @@ const struct rtos_register_stacking rtos_standard_Cortex_M4F_stacking = {
0x44, /* stack_registers_size 4 more for LR*/ 0x44, /* stack_registers_size 4 more for LR*/
-1, /* stack_growth_direction */ -1, /* stack_growth_direction */
ARMV7M_NUM_CORE_REGS, /* num_output_registers */ ARMV7M_NUM_CORE_REGS, /* num_output_registers */
rtos_standard_Cortex_M3_stack_align, /* stack_alignment */ rtos_standard_Cortex_M4F_stack_align, /* stack_alignment */
rtos_standard_Cortex_M4F_stack_offsets /* register_offsets */ rtos_standard_Cortex_M4F_stack_offsets /* register_offsets */
}; };
@ -249,7 +268,7 @@ const struct rtos_register_stacking rtos_standard_Cortex_M4F_FPU_stacking = {
0xcc, /* stack_registers_size 4 more for LR + 48 more for FPU S0-S15 register*/ 0xcc, /* stack_registers_size 4 more for LR + 48 more for FPU S0-S15 register*/
-1, /* stack_growth_direction */ -1, /* stack_growth_direction */
ARMV7M_NUM_CORE_REGS, /* num_output_registers */ ARMV7M_NUM_CORE_REGS, /* num_output_registers */
rtos_standard_Cortex_M3_stack_align, /* stack_alignment */ rtos_standard_Cortex_M4F_FPU_stack_align, /* stack_alignment */
rtos_standard_Cortex_M4F_FPU_stack_offsets /* register_offsets */ rtos_standard_Cortex_M4F_FPU_stack_offsets /* register_offsets */
}; };