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aarch64: unify armv7-a and armv8 debug entry decoding 

Make DSCR_RUN_MODE() usable for armv8 and arm7 debug

Change-Id: Ib3ba3000d5b6aa03e590f3ca4969e677474eb12c
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
This commit is contained in:
Matthias Welwarsky 2016-09-16 15:34:21 +02:00
parent e8602889f9
commit 4afa32ece1
4 changed files with 21 additions and 33 deletions
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8
src/target/aarch64.c
View File

@ -835,7 +835,7 @@ static int aarch64_poll(struct target *target)
return retval;
aarch64->cpudbg_dscr = dscr;
if (DSCR_RUN_MODE(dscr) == (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED)) {
if (DSCR_RUN_MODE(dscr) == 0x3) {
if (prev_target_state != TARGET_HALTED) {
/* We have a halting debug event */
LOG_DEBUG("Target halted");
@ -870,12 +870,8 @@ static int aarch64_poll(struct target *target)
TARGET_EVENT_DEBUG_HALTED);
}
}
} else if (DSCR_RUN_MODE(dscr) == DSCR_CORE_RESTARTED)
} else
target->state = TARGET_RUNNING;
else {
LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr);
target->state = TARGET_UNKNOWN;
}
return retval;
}

16
src/target/arm_dpm.c
View File

@ -930,20 +930,16 @@ void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
/* Examine debug reason */
switch (DSCR_ENTRY(dscr)) {
case 6: /* Data abort (v6 only) */
case 7: /* Prefetch abort (v6 only) */
/* FALL THROUGH -- assume a v6 core in abort mode */
case 0: /* HALT request from debugger */
case 4: /* EDBGRQ */
case DSCR_ENTRY_HALT_REQ: /* HALT request from debugger */
case DSCR_ENTRY_EXT_DBG_REQ: /* EDBGRQ */
target->debug_reason = DBG_REASON_DBGRQ;
break;
case 1: /* HW breakpoint */
case 3: /* SW BKPT */
case 5: /* vector catch */
case DSCR_ENTRY_BREAKPOINT: /* HW breakpoint */
case DSCR_ENTRY_BKPT_INSTR: /* vector catch */
target->debug_reason = DBG_REASON_BREAKPOINT;
break;
case 2: /* asynch watchpoint */
case 10:/* precise watchpoint */
case DSCR_ENTRY_IMPRECISE_WATCHPT: /* asynch watchpoint */
case DSCR_ENTRY_PRECISE_WATCHPT:/* precise watchpoint */
target->debug_reason = DBG_REASON_WATCHPOINT;
break;
default:

24
src/target/arm_dpm.h
View File

@ -186,21 +186,21 @@ void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
#define DSCR_DTR_TX_FULL (0x1 << 29)
#define DSCR_DTR_RX_FULL (0x1 << 30) /* bit 31 is reserved */
#define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf)
#define DSCR_RUN_MODE(dscr) ((dscr) & (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED))
#define DSCR_ENTRY(dscr) ((dscr) & 0x3f)
#define DSCR_RUN_MODE(dscr) ((dscr) & 0x03)
/* Methods of entry into debug mode */
#define DSCR_ENTRY_HALT_REQ (0x0 << 2)
#define DSCR_ENTRY_BREAKPOINT (0x1 << 2)
#define DSCR_ENTRY_IMPRECISE_WATCHPT (0x2 << 2)
#define DSCR_ENTRY_BKPT_INSTR (0x3 << 2)
#define DSCR_ENTRY_EXT_DBG_REQ (0x4 << 2)
#define DSCR_ENTRY_VECT_CATCH (0x5 << 2)
#define DSCR_ENTRY_D_SIDE_ABORT (0x6 << 2) /* v6 only */
#define DSCR_ENTRY_I_SIDE_ABORT (0x7 << 2) /* v6 only */
#define DSCR_ENTRY_OS_UNLOCK (0x8 << 2)
#define DSCR_ENTRY_PRECISE_WATCHPT (0xA << 2)
#define DSCR_ENTRY_HALT_REQ (0x03)
#define DSCR_ENTRY_BREAKPOINT (0x07)
#define DSCR_ENTRY_IMPRECISE_WATCHPT (0x0B)
#define DSCR_ENTRY_BKPT_INSTR (0x0F)
#define DSCR_ENTRY_EXT_DBG_REQ (0x13)
#define DSCR_ENTRY_VECT_CATCH (0x17)
#define DSCR_ENTRY_D_SIDE_ABORT (0x1B) /* v6 only */
#define DSCR_ENTRY_I_SIDE_ABORT (0x1F) /* v6 only */
#define DSCR_ENTRY_OS_UNLOCK (0x23)
#define DSCR_ENTRY_PRECISE_WATCHPT (0x2B)
/* DTR modes */
#define DSCR_EXT_DCC_NON_BLOCKING (0x0 << 20)

6
src/target/cortex_a.c
View File

@ -879,12 +879,8 @@ static int cortex_a_poll(struct target *target)
TARGET_EVENT_DEBUG_HALTED);
}
}
} else if (DSCR_RUN_MODE(dscr) == DSCR_CORE_RESTARTED)
} else
target->state = TARGET_RUNNING;
else {
LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr);
target->state = TARGET_UNKNOWN;
}
return retval;
}