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PXA255: force reset config 

These chips need both SRST and TRST when debugging,
and SRST doesn't gate JTAG.
This commit is contained in:
David Brownell 2009-10-26 22:59:46 -07:00
parent 4a91b070ff
commit 4a26390eec
1 changed files with 4 additions and 0 deletions
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4
tcl/target/pxa255.cfg
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@ -31,6 +31,10 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
jtag_khz 300 jtag_khz 300
$_TARGETNAME configure -event "reset-start" { jtag_khz 300 } $_TARGETNAME configure -event "reset-start" { jtag_khz 300 }
# both TRST and SRST are *required* for debug
# DCSR is often accessed with SRST active
reset_config trst_and_srst separate srst_nogate
# reset processing that works with PXA # reset processing that works with PXA
proc init_reset {mode} { proc init_reset {mode} {
# assert both resets; equivalent to power-on reset # assert both resets; equivalent to power-on reset