diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c index 1827c59db..2cb61f830 100644 --- a/src/target/adi_v5_swd.c +++ b/src/target/adi_v5_swd.c @@ -112,6 +112,8 @@ static int swd_connect(struct adiv5_dap *dap) /* Note, debugport_init() does setup too */ jtag_interface->swd->switch_seq(dap, JTAG_TO_SWD); + dap->do_reconnect = false; + swd_queue_dp_read(dap, DP_IDCODE, &idcode); /* force clear all sticky faults */ @@ -122,7 +124,8 @@ static int swd_connect(struct adiv5_dap *dap) if (status == ERROR_OK) { LOG_INFO("SWD IDCODE %#8.8" PRIx32, idcode); dap->do_reconnect = false; - } + } else + dap->do_reconnect = true; return status; } @@ -132,6 +135,14 @@ static inline int check_sync(struct adiv5_dap *dap) return do_sync ? swd_run_inner(dap) : ERROR_OK; } +static int swd_check_reconnect(struct adiv5_dap *dap) +{ + if (dap->do_reconnect) + return swd_connect(dap); + + return ERROR_OK; +} + static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack) { const struct swd_driver *swd = jtag_interface->swd; @@ -165,6 +176,10 @@ static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg, const struct swd_driver *swd = jtag_interface->swd; assert(swd); + int retval = swd_check_reconnect(dap); + if (retval != ERROR_OK) + return retval; + swd_queue_dp_bankselect(dap, reg); swd->read_reg(dap, swd_cmd(true, false, reg), data); @@ -177,6 +192,10 @@ static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg, const struct swd_driver *swd = jtag_interface->swd; assert(swd); + int retval = swd_check_reconnect(dap); + if (retval != ERROR_OK) + return retval; + swd_finish_read(dap); swd_queue_dp_bankselect(dap, reg); swd->write_reg(dap, swd_cmd(false, false, reg), data); @@ -204,11 +223,9 @@ static int swd_queue_ap_read(struct adiv5_dap *dap, unsigned reg, const struct swd_driver *swd = jtag_interface->swd; assert(swd); - if (dap->do_reconnect) { - int retval = swd_connect(dap); - if (retval != ERROR_OK) - return retval; - } + int retval = swd_check_reconnect(dap); + if (retval != ERROR_OK) + return retval; swd_queue_ap_bankselect(dap, reg); swd->read_reg(dap, swd_cmd(true, true, reg), dap->last_read); @@ -223,6 +240,10 @@ static int swd_queue_ap_write(struct adiv5_dap *dap, unsigned reg, const struct swd_driver *swd = jtag_interface->swd; assert(swd); + int retval = swd_check_reconnect(dap); + if (retval != ERROR_OK) + return retval; + swd_finish_read(dap); swd_queue_ap_bankselect(dap, reg); swd->write_reg(dap, swd_cmd(false, true, reg), data); diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 9234824d6..3e42af0a3 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -1053,12 +1053,6 @@ static int cortex_m_assert_reset(struct target *target) * This has the disadvantage of not resetting the peripherals, so a * reset-init event handler is needed to perform any peripheral resets. */ - retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, - AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ) - ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET)); - if (retval != ERROR_OK) - return retval; - LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ) ? "SYSRESETREQ" : "VECTRESET"); @@ -1067,17 +1061,16 @@ static int cortex_m_assert_reset(struct target *target) "handler to reset any peripherals or configure hardware srst support."); } - /* - SAM4L needs to execute security initalization - startup sequence before AP access would be enabled. - During the intialization CDBGPWRUPACK is pulled low and we - need to wait for it to be set to 1 again. - */ - retval = dap_dp_poll_register(swjdp, DP_CTRL_STAT, - CDBGPWRUPACK, CDBGPWRUPACK, 100); + retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, + AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ) + ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET)); + if (retval != ERROR_OK) + LOG_DEBUG("Ignoring AP write error right after reset"); + + retval = ahbap_debugport_init(swjdp); if (retval != ERROR_OK) { - LOG_ERROR("Failed waitnig for CDBGPWRUPACK"); - return ERROR_FAIL; + LOG_ERROR("DP initialisation failed"); + return retval; } {