a little bit more error handling in ARM11
git-svn-id: svn://svn.berlios.de/openocd/trunk@1542 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe
parent
e784db4fdd
commit
4866c8ed25
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@ -48,7 +48,7 @@
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#define FNC_INFO_NOTIMPLEMENTED
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#endif
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static void arm11_on_enter_debug_state(arm11_common_t * arm11);
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static int arm11_on_enter_debug_state(arm11_common_t * arm11);
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bool arm11_config_memwrite_burst = true;
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bool arm11_config_memwrite_error_fatal = true;
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@ -313,16 +313,18 @@ reg_t arm11_gdb_dummy_fps_reg =
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* available a pointer to a word holding the
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* DSCR can be passed. Otherwise use NULL.
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*/
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void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
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int arm11_check_init(arm11_common_t * arm11, u32 * dscr)
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{
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FNC_INFO;
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int retval;
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u32 dscr_local_tmp_copy;
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if (!dscr)
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{
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dscr = &dscr_local_tmp_copy;
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*dscr = arm11_read_DSCR(arm11);
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if ((retval=arm11_read_DSCR(arm11, dscr))!=ERROR_OK)
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return retval;
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}
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if (!(*dscr & ARM11_DSCR_MODE_SELECT))
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@ -353,6 +355,8 @@ void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
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arm11_sc7_clear_vbw(arm11);
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}
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return ERROR_OK;
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}
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@ -366,7 +370,7 @@ void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
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* or on other occasions that stop the processor.
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*
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*/
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static void arm11_on_enter_debug_state(arm11_common_t * arm11)
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static int arm11_on_enter_debug_state(arm11_common_t * arm11)
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{
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FNC_INFO;
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@ -378,8 +382,9 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
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}}
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/* Save DSCR */
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R(DSCR) = arm11_read_DSCR(arm11);
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int retval;
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if ((retval=arm11_read_DSCR(arm11, &R(DSCR)))!=ERROR_OK)
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return retval;
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/* Save wDTR */
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@ -514,6 +519,8 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
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arm11_run_instr_data_finish(arm11);
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arm11_dump_reg_changes(arm11);
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return ERROR_OK;
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}
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void arm11_dump_reg_changes(arm11_common_t * arm11)
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@ -546,7 +553,7 @@ void arm11_dump_reg_changes(arm11_common_t * arm11)
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* This is called in preparation for the RESTART function.
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*
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*/
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void arm11_leave_debug_state(arm11_common_t * arm11)
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int arm11_leave_debug_state(arm11_common_t * arm11)
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{
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FNC_INFO;
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@ -572,7 +579,12 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
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/* spec says clear wDTR and rDTR; we assume they are clear as
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otherwise our programming would be sloppy */
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{
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u32 DSCR = arm11_read_DSCR(arm11);
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u32 DSCR;
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int retval;
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if ((retval=arm11_read_DSCR(arm11, &DSCR))!=ERROR_OK)
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{
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return retval;
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}
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if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
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{
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@ -632,6 +644,8 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
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}
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arm11_record_register_history(arm11);
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return ERROR_OK;
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}
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void arm11_record_register_history(arm11_common_t * arm11)
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@ -658,11 +672,15 @@ int arm11_poll(struct target_s *target)
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if (arm11->trst_active)
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return ERROR_OK;
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u32 dscr = arm11_read_DSCR(arm11);
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u32 dscr;
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int retval;
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if ((retval=arm11_read_DSCR(arm11, &dscr))!=ERROR_OK)
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return retval;
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LOG_DEBUG("DSCR %08x", dscr);
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arm11_check_init(arm11, &dscr);
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if ((retval=arm11_check_init(arm11, &dscr))!=ERROR_OK)
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return retval;
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if (dscr & ARM11_DSCR_CORE_HALTED)
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{
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@ -747,7 +765,10 @@ int arm11_halt(struct target_s *target)
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while (1)
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{
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dscr = arm11_read_DSCR(arm11);
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int retval;
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retval = arm11_read_DSCR(arm11, &dscr);
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if (retval!=ERROR_OK)
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return retval;
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if (dscr & ARM11_DSCR_CORE_HALTED)
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break;
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@ -774,7 +795,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
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int retval = ERROR_OK;
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FNC_INFO;
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// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
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// current, address, handle_breakpoints, debug_execution);
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@ -851,7 +872,10 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
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while (1)
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{
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u32 dscr = arm11_read_DSCR(arm11);
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u32 dscr;
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retval = arm11_read_DSCR(arm11, &dscr);
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if (retval!=ERROR_OK)
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return retval;
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LOG_DEBUG("DSCR %08x", dscr);
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@ -961,7 +985,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
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R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
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else
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R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
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arm11_leave_debug_state(arm11);
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@ -978,7 +1002,10 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
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while (1)
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{
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u32 dscr = arm11_read_DSCR(arm11);
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u32 dscr;
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retval = arm11_read_DSCR(arm11, &dscr);
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if (retval!=ERROR_OK)
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return retval;
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LOG_DEBUG("DSCR %08x", dscr);
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@ -1987,7 +2014,7 @@ int arm11_register_commands(struct command_context_s *cmd_ctx)
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RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)",
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memrw_no_increment)
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RC_FINAL_BOOL( "step_irq_enable", "Enable interrupts while stepping (default: disabled)",
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step_irq_enable)
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@ -91,7 +91,7 @@ typedef struct arm11_common_s
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bool trst_active;
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bool halt_requested; /**< Keep track if arm11_halt() calls occured
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during reset. Otherwise do it ASAP. */
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bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
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/** \name Shadow registers to save processor state */
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@ -239,7 +239,7 @@ void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data,
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void arm11_add_IR (arm11_common_t * arm11, u8 instr, tap_state_t state);
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void arm11_add_debug_SCAN_N (arm11_common_t * arm11, u8 chain, tap_state_t state);
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void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state);
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u32 arm11_read_DSCR (arm11_common_t * arm11);
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int arm11_read_DSCR (arm11_common_t * arm11, u32 *dscr);
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void arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
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enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
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@ -216,7 +216,7 @@ void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state
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*
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* \remarks This is a stand-alone function that executes the JTAG command queue.
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*/
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u32 arm11_read_DSCR(arm11_common_t * arm11)
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int arm11_read_DSCR(arm11_common_t * arm11, u32 *value)
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{
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arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
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@ -229,14 +229,20 @@ u32 arm11_read_DSCR(arm11_common_t * arm11)
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arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
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jtag_execute_queue();
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int retval;
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if ((retval=jtag_execute_queue())!=ERROR_OK)
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{
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return retval;
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}
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if (arm11->last_dscr != dscr)
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JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
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arm11->last_dscr = dscr;
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return dscr;
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*value=dscr;
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return retval;
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}
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/** Write the Debug Status and Control Register (DSCR)
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