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Renamed mx2/imx27 to mxc. 

Renamed all functions, enums, structs and defines from mx2/imx27 to mxc. This is in preparation of adding support for mx35 NFC(v2).

Change-Id: I92ad23f0cfab605215bbf0d5846c5c288423facf
Signed-off-by: Erik Ahlén <erik.ahlen@avalonenterprise.com>
Reviewed-on: http://openocd.zylin.com/267
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
This commit is contained in:
Erik Ahlén 2011-12-13 10:24:11 +01:00 committed by Øyvind Harboe
parent c10a315f91
commit 46cc1df722
4 changed files with 244 additions and 243 deletions
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4
src/flash/nand/driver.c
View File

@ -38,7 +38,7 @@ extern struct nand_flash_controller s3c2412_nand_controller;
extern struct nand_flash_controller s3c2440_nand_controller; extern struct nand_flash_controller s3c2440_nand_controller;
extern struct nand_flash_controller s3c2443_nand_controller; extern struct nand_flash_controller s3c2443_nand_controller;
extern struct nand_flash_controller s3c6400_nand_controller; extern struct nand_flash_controller s3c6400_nand_controller;
extern struct nand_flash_controller imx27_nand_flash_controller; extern struct nand_flash_controller mxc_nand_flash_controller;
extern struct nand_flash_controller imx31_nand_flash_controller; extern struct nand_flash_controller imx31_nand_flash_controller;
extern struct nand_flash_controller at91sam9_nand_controller; extern struct nand_flash_controller at91sam9_nand_controller;
extern struct nand_flash_controller nuc910_nand_controller; extern struct nand_flash_controller nuc910_nand_controller;
@ -57,7 +57,7 @@ static struct nand_flash_controller *nand_flash_controllers[] =
&s3c2440_nand_controller, &s3c2440_nand_controller,
&s3c2443_nand_controller, &s3c2443_nand_controller,
&s3c6400_nand_controller, &s3c6400_nand_controller,
&imx27_nand_flash_controller, &mxc_nand_flash_controller,
&imx31_nand_flash_controller, &imx31_nand_flash_controller,
&at91sam9_nand_controller, &at91sam9_nand_controller,
&nuc910_nand_controller, &nuc910_nand_controller,

361
src/flash/nand/mx2.c
View File

@ -23,17 +23,17 @@
***************************************************************************/ ***************************************************************************/
/* /*
* Freescale iMX2* OpenOCD NAND Flash controller support. * Freescale iMX OpenOCD NAND Flash controller support.
* based on Freescale iMX3* OpenOCD NAND Flash controller support. * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
*/ */
/* /*
* driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @imx27 * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
* tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
* "nand write # file 0", "nand verify" * "nand write # file 0", "nand verify"
* *
* get_next_halfword_from_sram_buffer() not tested * get_next_halfword_from_sram_buffer() not tested
* !! all function only tested with 2k page nand device; imx27_write_page * !! all function only tested with 2k page nand device; mxc_write_page
* writes the 4 MAIN_BUFFER's and is not compatible with < 2k page * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
* !! oob must be be used due to NFS bug * !! oob must be be used due to NFS bug
*/ */
@ -50,11 +50,11 @@
* This is useful when OpenOCD is used with a graphical * This is useful when OpenOCD is used with a graphical
* front-end to estimate progression of the global read/write * front-end to estimate progression of the global read/write
*/ */
#undef _MX2_PRINT_STAT #undef _MXC_PRINT_STAT
/* #define _MX2_PRINT_STAT */ /* #define _MXC_PRINT_STAT */
static const char target_not_halted_err_msg[] = static const char target_not_halted_err_msg[] =
"target must be halted to use mx2 NAND flash controller"; "target must be halted to use mxc NAND flash controller";
static const char data_block_size_err_msg[] = static const char data_block_size_err_msg[] =
"minimal granularity is one half-word, %" PRId32 " is incorrect"; "minimal granularity is one half-word, %" PRId32 " is incorrect";
static const char sram_buffer_bounds_err_msg[] = static const char sram_buffer_bounds_err_msg[] =
@ -70,24 +70,24 @@ static int poll_for_complete_op(struct target *target, const char *text);
static int validate_target_state(struct nand_device *nand); static int validate_target_state(struct nand_device *nand);
static int do_data_output(struct nand_device *nand); static int do_data_output(struct nand_device *nand);
static int imx27_command(struct nand_device *nand, uint8_t command); static int mxc_command(struct nand_device *nand, uint8_t command);
static int imx27_address(struct nand_device *nand, uint8_t address); static int mxc_address(struct nand_device *nand, uint8_t address);
NAND_DEVICE_COMMAND_HANDLER(imx27_nand_device_command) NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
{ {
struct mx2_nf_controller *mx2_nf_info; struct mxc_nf_controller *mxc_nf_info;
int hwecc_needed; int hwecc_needed;
int x; int x;
mx2_nf_info = malloc(sizeof(struct mx2_nf_controller)); mxc_nf_info = malloc(sizeof(struct mxc_nf_controller));
if (mx2_nf_info == NULL) { if (mxc_nf_info == NULL) {
LOG_ERROR("no memory for nand controller"); LOG_ERROR("no memory for nand controller");
return ERROR_FAIL; return ERROR_FAIL;
} }
nand->controller_priv = mx2_nf_info; nand->controller_priv = mxc_nf_info;
if (CMD_ARGC < 3) { if (CMD_ARGC < 3) {
LOG_ERROR("use \"nand device imx27 target noecc|hwecc\""); LOG_ERROR("use \"nand device mxc target noecc|hwecc\"");
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -96,13 +96,13 @@ NAND_DEVICE_COMMAND_HANDLER(imx27_nand_device_command)
*/ */
hwecc_needed = strcmp(CMD_ARGV[2], "hwecc"); hwecc_needed = strcmp(CMD_ARGV[2], "hwecc");
if (hwecc_needed == 0) if (hwecc_needed == 0)
mx2_nf_info->flags.hw_ecc_enabled = 1; mxc_nf_info->flags.hw_ecc_enabled = 1;
else else
mx2_nf_info->flags.hw_ecc_enabled = 0; mxc_nf_info->flags.hw_ecc_enabled = 0;
mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE; mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
mx2_nf_info->fin = MX2_NF_FIN_NONE; mxc_nf_info->fin = MXC_NF_FIN_NONE;
mx2_nf_info->flags.target_little_endian = mxc_nf_info->flags.target_little_endian =
(nand->target->endianness == TARGET_LITTLE_ENDIAN); (nand->target->endianness == TARGET_LITTLE_ENDIAN);
/* /*
@ -110,15 +110,15 @@ NAND_DEVICE_COMMAND_HANDLER(imx27_nand_device_command)
*/ */
x = 1; x = 1;
if (*(char *) &x == 1) if (*(char *) &x == 1)
mx2_nf_info->flags.host_little_endian = 1; mxc_nf_info->flags.host_little_endian = 1;
else else
mx2_nf_info->flags.host_little_endian = 0; mxc_nf_info->flags.host_little_endian = 0;
return ERROR_OK; return ERROR_OK;
} }
static int imx27_init(struct nand_device *nand) static int mxc_init(struct nand_device *nand)
{ {
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv; struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
struct target *target = nand->target; struct target *target = nand->target;
int validate_target_result; int validate_target_result;
@ -133,60 +133,60 @@ static int imx27_init(struct nand_device *nand)
if (validate_target_result != ERROR_OK) if (validate_target_result != ERROR_OK)
return validate_target_result; return validate_target_result;
target_read_u16(target, MX2_NF_BUFSIZ, &buffsize_register_content); target_read_u16(target, MXC_NF_BUFSIZ, &buffsize_register_content);
mx2_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f); mxc_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
target_read_u32(target, MX2_FMCR, &pcsr_register_content); target_read_u32(target, MXC_FMCR, &pcsr_register_content);
if (!nand->bus_width) { if (!nand->bus_width) {
/* bus_width not yet defined. Read it from MX2_FMCR */ /* bus_width not yet defined. Read it from MXC_FMCR */
nand->bus_width = nand->bus_width =
(pcsr_register_content & MX2_FMCR_NF_16BIT_SEL) ? 16 : 8; (pcsr_register_content & MXC_FMCR_NF_16BIT_SEL) ? 16 : 8;
} else { } else {
/* bus_width forced in soft. Sync it to MX2_FMCR */ /* bus_width forced in soft. Sync it to MXC_FMCR */
pcsr_register_content |= pcsr_register_content |=
((nand->bus_width == 16) ? MX2_FMCR_NF_16BIT_SEL : 0x00000000); ((nand->bus_width == 16) ? MXC_FMCR_NF_16BIT_SEL : 0x00000000);
target_write_u32(target, MX2_FMCR, pcsr_register_content); target_write_u32(target, MXC_FMCR, pcsr_register_content);
} }
if (nand->bus_width == 16) if (nand->bus_width == 16)
LOG_DEBUG("MX2_NF : bus is 16-bit width"); LOG_DEBUG("MXC_NF : bus is 16-bit width");
else else
LOG_DEBUG("MX2_NF : bus is 8-bit width"); LOG_DEBUG("MXC_NF : bus is 8-bit width");
if (!nand->page_size) { if (!nand->page_size) {
nand->page_size = (pcsr_register_content & MX2_FMCR_NF_FMS) ? 2048 : 512; nand->page_size = (pcsr_register_content & MXC_FMCR_NF_FMS) ? 2048 : 512;
} else { } else {
pcsr_register_content |= pcsr_register_content |=
((nand->page_size == 2048) ? MX2_FMCR_NF_FMS : 0x00000000); ((nand->page_size == 2048) ? MXC_FMCR_NF_FMS : 0x00000000);
target_write_u32(target, MX2_FMCR, pcsr_register_content); target_write_u32(target, MXC_FMCR, pcsr_register_content);
} }
if (mx2_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) { if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
LOG_ERROR("NAND controller have only 1 kb SRAM, so " LOG_ERROR("NAND controller have only 1 kb SRAM, so "
"pagesize 2048 is incompatible with it"); "pagesize 2048 is incompatible with it");
} else { } else {
LOG_DEBUG("MX2_NF : NAND controller can handle pagesize of 2048"); LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
} }
initialize_nf_controller(nand); initialize_nf_controller(nand);
retval = ERROR_OK; retval = ERROR_OK;
retval |= imx27_command(nand, NAND_CMD_STATUS); retval |= mxc_command(nand, NAND_CMD_STATUS);
retval |= imx27_address(nand, 0x00); retval |= mxc_address(nand, 0x00);
retval |= do_data_output(nand); retval |= do_data_output(nand);
if (retval != ERROR_OK) { if (retval != ERROR_OK) {
LOG_ERROR(get_status_register_err_msg); LOG_ERROR(get_status_register_err_msg);
return ERROR_FAIL; return ERROR_FAIL;
} }
target_read_u16(target, MX2_NF_MAIN_BUFFER0, &nand_status_content); target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
if (!(nand_status_content & 0x0080)) { if (!(nand_status_content & 0x0080)) {
LOG_INFO("NAND read-only"); LOG_INFO("NAND read-only");
mx2_nf_info->flags.nand_readonly = 1; mxc_nf_info->flags.nand_readonly = 1;
} else { } else {
mx2_nf_info->flags.nand_readonly = 0; mxc_nf_info->flags.nand_readonly = 0;
} }
return ERROR_OK; return ERROR_OK;
} }
static int imx27_read_data(struct nand_device *nand, void *data) static int mxc_read_data(struct nand_device *nand, void *data)
{ {
struct target *target = nand->target; struct target *target = nand->target;
int validate_target_result; int validate_target_result;
@ -203,7 +203,7 @@ static int imx27_read_data(struct nand_device *nand, void *data)
*/ */
try_data_output_from_nand_chip = do_data_output(nand); try_data_output_from_nand_chip = do_data_output(nand);
if (try_data_output_from_nand_chip != ERROR_OK) { if (try_data_output_from_nand_chip != ERROR_OK) {
LOG_ERROR("imx27_read_data : read data failed : '%x'", LOG_ERROR("mxc_read_data : read data failed : '%x'",
try_data_output_from_nand_chip); try_data_output_from_nand_chip);
return try_data_output_from_nand_chip; return try_data_output_from_nand_chip;
} }
@ -216,13 +216,13 @@ static int imx27_read_data(struct nand_device *nand, void *data)
return ERROR_OK; return ERROR_OK;
} }
static int imx27_write_data(struct nand_device *nand, uint16_t data) static int mxc_write_data(struct nand_device *nand, uint16_t data)
{ {
LOG_ERROR("write_data() not implemented"); LOG_ERROR("write_data() not implemented");
return ERROR_NAND_OPERATION_FAILED; return ERROR_NAND_OPERATION_FAILED;
} }
static int imx27_reset(struct nand_device *nand) static int mxc_reset(struct nand_device *nand)
{ {
/* /*
* validate target state * validate target state
@ -235,9 +235,9 @@ static int imx27_reset(struct nand_device *nand)
return ERROR_OK; return ERROR_OK;
} }
static int imx27_command(struct nand_device *nand, uint8_t command) static int mxc_command(struct nand_device *nand, uint8_t command)
{ {
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv; struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
struct target *target = nand->target; struct target *target = nand->target;
int validate_target_result; int validate_target_result;
int poll_result; int poll_result;
@ -254,25 +254,25 @@ static int imx27_command(struct nand_device *nand, uint8_t command)
/* set read point for data_read() and read_block_data() to /* set read point for data_read() and read_block_data() to
* spare area in SRAM buffer * spare area in SRAM buffer
*/ */
in_sram_address = MX2_NF_SPARE_BUFFER0; in_sram_address = MXC_NF_SPARE_BUFFER0;
break; break;
case NAND_CMD_READ1: case NAND_CMD_READ1:
command = NAND_CMD_READ0; command = NAND_CMD_READ0;
/* /*
* offset == one half of page size * offset == one half of page size
*/ */
in_sram_address = MX2_NF_MAIN_BUFFER0 + (nand->page_size >> 1); in_sram_address = MXC_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
break; break;
default: default:
in_sram_address = MX2_NF_MAIN_BUFFER0; in_sram_address = MXC_NF_MAIN_BUFFER0;
break; break;
} }
target_write_u16(target, MX2_NF_FCMD, command); target_write_u16(target, MXC_NF_FCMD, command);
/* /*
* start command input operation (set MX2_NF_BIT_OP_DONE==0) * start command input operation (set MXC_NF_BIT_OP_DONE==0)
*/ */
target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FCI); target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FCI);
poll_result = poll_for_complete_op(target, "command"); poll_result = poll_for_complete_op(target, "command");
if (poll_result != ERROR_OK) if (poll_result != ERROR_OK)
return poll_result; return poll_result;
@ -283,28 +283,28 @@ static int imx27_command(struct nand_device *nand, uint8_t command)
/* Handle special read command and adjust NF_CFG2(FDO) */ /* Handle special read command and adjust NF_CFG2(FDO) */
switch (command) { switch (command) {
case NAND_CMD_READID: case NAND_CMD_READID:
mx2_nf_info->optype = MX2_NF_DATAOUT_NANDID; mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
mx2_nf_info->fin = MX2_NF_FIN_DATAOUT; mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
break; break;
case NAND_CMD_STATUS: case NAND_CMD_STATUS:
mx2_nf_info->optype = MX2_NF_DATAOUT_NANDSTATUS; mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
mx2_nf_info->fin = MX2_NF_FIN_DATAOUT; mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
target_write_u16 (target, MX2_NF_BUFADDR, 0); target_write_u16 (target, MXC_NF_BUFADDR, 0);
in_sram_address = 0; in_sram_address = 0;
break; break;
case NAND_CMD_READ0: case NAND_CMD_READ0:
mx2_nf_info->fin = MX2_NF_FIN_DATAOUT; mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE; mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
break; break;
default: default:
/* Ohter command use the default 'One page data out' FDO */ /* Ohter command use the default 'One page data out' FDO */
mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE; mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
break; break;
} }
return ERROR_OK; return ERROR_OK;
} }
static int imx27_address(struct nand_device *nand, uint8_t address) static int mxc_address(struct nand_device *nand, uint8_t address)
{ {
struct target *target = nand->target; struct target *target = nand->target;
int validate_target_result; int validate_target_result;
@ -316,11 +316,11 @@ static int imx27_address(struct nand_device *nand, uint8_t address)
if (validate_target_result != ERROR_OK) if (validate_target_result != ERROR_OK)
return validate_target_result; return validate_target_result;
target_write_u16(target, MX2_NF_FADDR, address); target_write_u16(target, MXC_NF_FADDR, address);
/* /*
* start address input operation (set MX2_NF_BIT_OP_DONE==0) * start address input operation (set MXC_NF_BIT_OP_DONE==0)
*/ */
target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FAI); target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FAI);
poll_result = poll_for_complete_op(target, "address"); poll_result = poll_for_complete_op(target, "address");
if (poll_result != ERROR_OK) if (poll_result != ERROR_OK)
return poll_result; return poll_result;
@ -328,7 +328,7 @@ static int imx27_address(struct nand_device *nand, uint8_t address)
return ERROR_OK; return ERROR_OK;
} }
static int imx27_nand_ready(struct nand_device *nand, int tout) static int mxc_nand_ready(struct nand_device *nand, int tout)
{ {
uint16_t poll_complete_status; uint16_t poll_complete_status;
struct target *target = nand->target; struct target *target = nand->target;
@ -342,8 +342,8 @@ static int imx27_nand_ready(struct nand_device *nand, int tout)
return validate_target_result; return validate_target_result;
do { do {
target_read_u16(target, MX2_NF_CFG2, &poll_complete_status); target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
if (poll_complete_status & MX2_NF_BIT_OP_DONE) if (poll_complete_status & MXC_NF_BIT_OP_DONE)
return tout; return tout;
alive_sleep(1); alive_sleep(1);
@ -352,11 +352,11 @@ static int imx27_nand_ready(struct nand_device *nand, int tout)
return tout; return tout;
} }
static int imx27_write_page(struct nand_device *nand, uint32_t page, static int mxc_write_page(struct nand_device *nand, uint32_t page,
uint8_t *data, uint32_t data_size, uint8_t *data, uint32_t data_size,
uint8_t *oob, uint32_t oob_size) uint8_t *oob, uint32_t oob_size)
{ {
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv; struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
struct target *target = nand->target; struct target *target = nand->target;
int retval; int retval;
uint16_t nand_status_content; uint16_t nand_status_content;
@ -381,19 +381,19 @@ static int imx27_write_page(struct nand_device *nand, uint32_t page,
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
in_sram_address = MX2_NF_MAIN_BUFFER0; in_sram_address = MXC_NF_MAIN_BUFFER0;
sign_of_sequental_byte_read = 0; sign_of_sequental_byte_read = 0;
retval = ERROR_OK; retval = ERROR_OK;
retval |= imx27_command(nand, NAND_CMD_SEQIN); retval |= mxc_command(nand, NAND_CMD_SEQIN);
retval |= imx27_address(nand, 0); /* col */ retval |= mxc_address(nand, 0); /* col */
retval |= imx27_address(nand, 0); /* col */ retval |= mxc_address(nand, 0); /* col */
retval |= imx27_address(nand, page & 0xff); /* page address */ retval |= mxc_address(nand, page & 0xff); /* page address */
retval |= imx27_address(nand, (page >> 8) & 0xff); /* page address */ retval |= mxc_address(nand, (page >> 8) & 0xff); /* page address */
retval |= imx27_address(nand, (page >> 16) & 0xff); /* page address */ retval |= mxc_address(nand, (page >> 16) & 0xff); /* page address */
target_write_buffer(target, MX2_NF_MAIN_BUFFER0, data_size, data); target_write_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
if (oob) { if (oob) {
if (mx2_nf_info->flags.hw_ecc_enabled) { if (mxc_nf_info->flags.hw_ecc_enabled) {
/* /*
* part of spare block will be overrided by hardware * part of spare block will be overrided by hardware
* ECC generator * ECC generator
@ -401,48 +401,48 @@ static int imx27_write_page(struct nand_device *nand, uint32_t page,
LOG_DEBUG("part of spare block will be overrided " LOG_DEBUG("part of spare block will be overrided "
"by hardware ECC generator"); "by hardware ECC generator");
} }
target_write_buffer(target, MX2_NF_SPARE_BUFFER0, oob_size, oob); target_write_buffer(target, MXC_NF_SPARE_BUFFER0, oob_size, oob);
} }
/* BI-swap - work-around of imx27 NFC for NAND device with page == 2kb */ /* BI-swap - work-around of mxc NFC for NAND device with page == 2kb */
target_read_u16(target, MX2_NF_MAIN_BUFFER3 + 464, &swap1); target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
if (oob) { if (oob) {
LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mx2 driver"); LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
return ERROR_NAND_OPERATION_FAILED; return ERROR_NAND_OPERATION_FAILED;
} }
swap2 = 0xffff; /* Spare buffer unused forced to 0xffff */ swap2 = 0xffff; /* Spare buffer unused forced to 0xffff */
new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8); new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
swap2 = (swap1 << 8) | (swap2 & 0xFF); swap2 = (swap1 << 8) | (swap2 & 0xFF);
target_write_u16(target, MX2_NF_MAIN_BUFFER3 + 464, new_swap1); target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
target_write_u16(target, MX2_NF_SPARE_BUFFER3 + 4, swap2); target_write_u16(target, MXC_NF_SPARE_BUFFER3 + 4, swap2);
/* /*
* start data input operation (set MX2_NF_BIT_OP_DONE==0) * start data input operation (set MXC_NF_BIT_OP_DONE==0)
*/ */
target_write_u16(target, MX2_NF_BUFADDR, 0); target_write_u16(target, MXC_NF_BUFADDR, 0);
target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI); target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
poll_result = poll_for_complete_op(target, "data input"); poll_result = poll_for_complete_op(target, "data input");
if (poll_result != ERROR_OK) if (poll_result != ERROR_OK)
return poll_result; return poll_result;
target_write_u16(target, MX2_NF_BUFADDR, 1); target_write_u16(target, MXC_NF_BUFADDR, 1);
target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI); target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
poll_result = poll_for_complete_op(target, "data input"); poll_result = poll_for_complete_op(target, "data input");
if (poll_result != ERROR_OK) if (poll_result != ERROR_OK)
return poll_result; return poll_result;
target_write_u16(target, MX2_NF_BUFADDR, 2); target_write_u16(target, MXC_NF_BUFADDR, 2);
target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI); target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
poll_result = poll_for_complete_op(target, "data input"); poll_result = poll_for_complete_op(target, "data input");
if (poll_result != ERROR_OK) if (poll_result != ERROR_OK)
return poll_result; return poll_result;
target_write_u16(target, MX2_NF_BUFADDR, 3); target_write_u16(target, MXC_NF_BUFADDR, 3);
target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI); target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
poll_result = poll_for_complete_op(target, "data input"); poll_result = poll_for_complete_op(target, "data input");
if (poll_result != ERROR_OK) if (poll_result != ERROR_OK)
return poll_result; return poll_result;
retval |= imx27_command(nand, NAND_CMD_PAGEPROG); retval |= mxc_command(nand, NAND_CMD_PAGEPROG);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
@ -450,33 +450,33 @@ static int imx27_write_page(struct nand_device *nand, uint32_t page,
* check status register * check status register
*/ */
retval = ERROR_OK; retval = ERROR_OK;
retval |= imx27_command(nand, NAND_CMD_STATUS); retval |= mxc_command(nand, NAND_CMD_STATUS);
target_write_u16 (target, MX2_NF_BUFADDR, 0); target_write_u16 (target, MXC_NF_BUFADDR, 0);
mx2_nf_info->optype = MX2_NF_DATAOUT_NANDSTATUS; mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
mx2_nf_info->fin = MX2_NF_FIN_DATAOUT; mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
retval |= do_data_output(nand); retval |= do_data_output(nand);
if (retval != ERROR_OK) { if (retval != ERROR_OK) {
LOG_ERROR(get_status_register_err_msg); LOG_ERROR(get_status_register_err_msg);
return retval; return retval;
} }
target_read_u16(target, MX2_NF_MAIN_BUFFER0, &nand_status_content); target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
if (nand_status_content & 0x0001) { if (nand_status_content & 0x0001) {
/* /*
* page not correctly written * page not correctly written
*/ */
return ERROR_NAND_OPERATION_FAILED; return ERROR_NAND_OPERATION_FAILED;
} }
#ifdef _MX2_PRINT_STAT #ifdef _MXC_PRINT_STAT
LOG_INFO("%d bytes newly written", data_size); LOG_INFO("%d bytes newly written", data_size);
#endif #endif
return ERROR_OK; return ERROR_OK;
} }
static int imx27_read_page(struct nand_device *nand, uint32_t page, static int mxc_read_page(struct nand_device *nand, uint32_t page,
uint8_t *data, uint32_t data_size, uint8_t *data, uint32_t data_size,
uint8_t *oob, uint32_t oob_size) uint8_t *oob, uint32_t oob_size)
{ {
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv; struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
struct target *target = nand->target; struct target *target = nand->target;
int retval; int retval;
uint16_t swap1, swap2, new_swap1; uint16_t swap1, swap2, new_swap1;
@ -497,65 +497,65 @@ static int imx27_read_page(struct nand_device *nand, uint32_t page,
if (retval != ERROR_OK) { if (retval != ERROR_OK) {
return retval; return retval;
} }
/* Reset address_cycles before imx27_command ?? */ /* Reset address_cycles before mxc_command ?? */
retval = imx27_command(nand, NAND_CMD_READ0); retval = mxc_command(nand, NAND_CMD_READ0);
if (retval != ERROR_OK) return retval; if (retval != ERROR_OK) return retval;
retval = imx27_address(nand, 0); /* col */ retval = mxc_address(nand, 0); /* col */
if (retval != ERROR_OK) return retval; if (retval != ERROR_OK) return retval;
retval = imx27_address(nand, 0); /* col */ retval = mxc_address(nand, 0); /* col */
if (retval != ERROR_OK) return retval; if (retval != ERROR_OK) return retval;
retval = imx27_address(nand, page & 0xff); /* page address */ retval = mxc_address(nand, page & 0xff); /* page address */
if (retval != ERROR_OK) return retval; if (retval != ERROR_OK) return retval;
retval = imx27_address(nand, (page >> 8) & 0xff); /* page address */ retval = mxc_address(nand, (page >> 8) & 0xff); /* page address */
if (retval != ERROR_OK) return retval; if (retval != ERROR_OK) return retval;
retval = imx27_address(nand, (page >> 16) & 0xff); /* page address */ retval = mxc_address(nand, (page >> 16) & 0xff); /* page address */
if (retval != ERROR_OK) return retval; if (retval != ERROR_OK) return retval;
retval = imx27_command(nand, NAND_CMD_READSTART); retval = mxc_command(nand, NAND_CMD_READSTART);
if (retval != ERROR_OK) return retval; if (retval != ERROR_OK) return retval;
target_write_u16(target, MX2_NF_BUFADDR, 0); target_write_u16(target, MXC_NF_BUFADDR, 0);
mx2_nf_info->fin = MX2_NF_FIN_DATAOUT; mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
retval = do_data_output(nand); retval = do_data_output(nand);
if (retval != ERROR_OK) { if (retval != ERROR_OK) {
LOG_ERROR("MX2_NF : Error reading page 0"); LOG_ERROR("MXC_NF : Error reading page 0");
return retval; return retval;
} }
/* Test nand page size to know how much MAIN_BUFFER must be written */ /* Test nand page size to know how much MAIN_BUFFER must be written */
target_write_u16(target, MX2_NF_BUFADDR, 1); target_write_u16(target, MXC_NF_BUFADDR, 1);
mx2_nf_info->fin = MX2_NF_FIN_DATAOUT; mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
retval = do_data_output(nand); retval = do_data_output(nand);
if (retval != ERROR_OK) { if (retval != ERROR_OK) {
LOG_ERROR("MX2_NF : Error reading page 1"); LOG_ERROR("MXC_NF : Error reading page 1");
return retval; return retval;
} }
target_write_u16(target, MX2_NF_BUFADDR, 2); target_write_u16(target, MXC_NF_BUFADDR, 2);
mx2_nf_info->fin = MX2_NF_FIN_DATAOUT; mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
retval = do_data_output(nand); retval = do_data_output(nand);
if (retval != ERROR_OK) { if (retval != ERROR_OK) {
LOG_ERROR("MX2_NF : Error reading page 2"); LOG_ERROR("MXC_NF : Error reading page 2");
return retval; return retval;
} }
target_write_u16(target, MX2_NF_BUFADDR, 3); target_write_u16(target, MXC_NF_BUFADDR, 3);
mx2_nf_info->fin = MX2_NF_FIN_DATAOUT; mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
retval = do_data_output(nand); retval = do_data_output(nand);
if (retval != ERROR_OK) { if (retval != ERROR_OK) {
LOG_ERROR("MX2_NF : Error reading page 3"); LOG_ERROR("MXC_NF : Error reading page 3");
return retval; return retval;
} }
/* BI-swap - work-around of imx27 NFC for NAND device with page == 2k */ /* BI-swap - work-around of mxc NFC for NAND device with page == 2k */
target_read_u16(target, MX2_NF_MAIN_BUFFER3 + 464, &swap1); target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
target_read_u16(target, MX2_NF_SPARE_BUFFER3 + 4, &swap2); target_read_u16(target, MXC_NF_SPARE_BUFFER3 + 4, &swap2);
new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8); new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
swap2 = (swap1 << 8) | (swap2 & 0xFF); swap2 = (swap1 << 8) | (swap2 & 0xFF);
target_write_u16(target, MX2_NF_MAIN_BUFFER3 + 464, new_swap1); target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
target_write_u16(target, MX2_NF_SPARE_BUFFER3 + 4, swap2); target_write_u16(target, MXC_NF_SPARE_BUFFER3 + 4, swap2);
if (data) if (data)
target_read_buffer(target, MX2_NF_MAIN_BUFFER0, data_size, data); target_read_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
if (oob) if (oob)
target_read_buffer(target, MX2_NF_SPARE_BUFFER0, oob_size, oob); target_read_buffer(target, MXC_NF_SPARE_BUFFER0, oob_size, oob);
#ifdef _MX2_PRINT_STAT #ifdef _MXC_PRINT_STAT
if (data_size > 0) { if (data_size > 0) {
/* When Operation Status is read (when page is erased), /* When Operation Status is read (when page is erased),
* this function is used but data_size is null. * this function is used but data_size is null.
@ -568,33 +568,33 @@ static int imx27_read_page(struct nand_device *nand, uint32_t page,
static int initialize_nf_controller(struct nand_device *nand) static int initialize_nf_controller(struct nand_device *nand)
{ {
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv; struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
struct target *target = nand->target; struct target *target = nand->target;
uint16_t work_mode; uint16_t work_mode;
uint16_t temp; uint16_t temp;
/* /*
* resets NAND flash controller in zero time ? I dont know. * resets NAND flash controller in zero time ? I dont know.
*/ */
target_write_u16(target, MX2_NF_CFG1, MX2_NF_BIT_RESET_EN); target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
work_mode = MX2_NF_BIT_INT_DIS; /* disable interrupt */ work_mode = MXC_NF_BIT_INT_DIS; /* disable interrupt */
if (target->endianness == TARGET_BIG_ENDIAN) { if (target->endianness == TARGET_BIG_ENDIAN) {
LOG_DEBUG("MX2_NF : work in Big Endian mode"); LOG_DEBUG("MXC_NF : work in Big Endian mode");
work_mode |= MX2_NF_BIT_BE_EN; work_mode |= MXC_NF_BIT_BE_EN;
} else { } else {
LOG_DEBUG("MX2_NF : work in Little Endian mode"); LOG_DEBUG("MXC_NF : work in Little Endian mode");
} }
if (mx2_nf_info->flags.hw_ecc_enabled) { if (mxc_nf_info->flags.hw_ecc_enabled) {
LOG_DEBUG("MX2_NF : work with ECC mode"); LOG_DEBUG("MXC_NF : work with ECC mode");
work_mode |= MX2_NF_BIT_ECC_EN; work_mode |= MXC_NF_BIT_ECC_EN;
} else { } else {
LOG_DEBUG("MX2_NF : work without ECC mode"); LOG_DEBUG("MXC_NF : work without ECC mode");
} }
target_write_u16(target, MX2_NF_CFG1, work_mode); target_write_u16(target, MXC_NF_CFG1, work_mode);
/* /*
* unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock" * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
*/ */
target_write_u16(target, MX2_NF_BUFCFG, 2); target_write_u16(target, MXC_NF_BUFCFG, 2);
target_read_u16(target, MX2_NF_FWP, &temp); target_read_u16(target, MXC_NF_FWP, &temp);
if ((temp & 0x0007) == 1) { if ((temp & 0x0007) == 1) {
LOG_ERROR("NAND flash is tight-locked, reset needed"); LOG_ERROR("NAND flash is tight-locked, reset needed");
return ERROR_FAIL; return ERROR_FAIL;
@ -603,17 +603,17 @@ static int initialize_nf_controller(struct nand_device *nand)
/* /*
* unlock NAND flash for write * unlock NAND flash for write
*/ */
target_write_u16(target, MX2_NF_FWP, 4); target_write_u16(target, MXC_NF_FWP, 4);
target_write_u16(target, MX2_NF_LOCKSTART, 0x0000); target_write_u16(target, MXC_NF_LOCKSTART, 0x0000);
target_write_u16(target, MX2_NF_LOCKEND, 0xFFFF); target_write_u16(target, MXC_NF_LOCKEND, 0xFFFF);
/* /*
* 0x0000 means that first SRAM buffer @0xD800_0000 will be used * 0x0000 means that first SRAM buffer @0xD800_0000 will be used
*/ */
target_write_u16(target, MX2_NF_BUFADDR, 0x0000); target_write_u16(target, MXC_NF_BUFADDR, 0x0000);
/* /*
* address of SRAM buffer * address of SRAM buffer
*/ */
in_sram_address = MX2_NF_MAIN_BUFFER0; in_sram_address = MXC_NF_MAIN_BUFFER0;
sign_of_sequental_byte_read = 0; sign_of_sequental_byte_read = 0;
return ERROR_OK; return ERROR_OK;
} }
@ -628,7 +628,7 @@ static int get_next_byte_from_sram_buffer(struct target *target, uint8_t *value)
if (sign_of_sequental_byte_read == 0) if (sign_of_sequental_byte_read == 0)
even_byte = 0; even_byte = 0;
if (in_sram_address > MX2_NF_LAST_BUFFER_ADDR) { if (in_sram_address > MXC_NF_LAST_BUFFER_ADDR) {
LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address); LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
*value = 0; *value = 0;
sign_of_sequental_byte_read = 0; sign_of_sequental_byte_read = 0;
@ -651,7 +651,7 @@ static int get_next_byte_from_sram_buffer(struct target *target, uint8_t *value)
static int get_next_halfword_from_sram_buffer(struct target *target, uint16_t *value) static int get_next_halfword_from_sram_buffer(struct target *target, uint16_t *value)
{ {
if (in_sram_address > MX2_NF_LAST_BUFFER_ADDR) { if (in_sram_address > MXC_NF_LAST_BUFFER_ADDR) {
LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address); LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
*value = 0; *value = 0;
return ERROR_NAND_OPERATION_FAILED; return ERROR_NAND_OPERATION_FAILED;
@ -666,13 +666,13 @@ static int poll_for_complete_op(struct target *target, const char *text)
{ {
uint16_t poll_complete_status; uint16_t poll_complete_status;
for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) { for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) {
target_read_u16(target, MX2_NF_CFG2, &poll_complete_status); target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
if (poll_complete_status & MX2_NF_BIT_OP_DONE) if (poll_complete_status & MXC_NF_BIT_OP_DONE)
break; break;
usleep(10); usleep(10);
} }
if (!(poll_complete_status & MX2_NF_BIT_OP_DONE)) { if (!(poll_complete_status & MXC_NF_BIT_OP_DONE)) {
LOG_ERROR("%s sending timeout", text); LOG_ERROR("%s sending timeout", text);
return ERROR_NAND_OPERATION_FAILED; return ERROR_NAND_OPERATION_FAILED;
} }
@ -681,7 +681,7 @@ static int poll_for_complete_op(struct target *target, const char *text)
static int validate_target_state(struct nand_device *nand) static int validate_target_state(struct nand_device *nand)
{ {
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv; struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
struct target *target = nand->target; struct target *target = nand->target;
if (target->state != TARGET_HALTED) { if (target->state != TARGET_HALTED) {
@ -689,7 +689,7 @@ static int validate_target_state(struct nand_device *nand)
return ERROR_NAND_OPERATION_FAILED; return ERROR_NAND_OPERATION_FAILED;
} }
if (mx2_nf_info->flags.target_little_endian != if (mxc_nf_info->flags.target_little_endian !=
(target->endianness == TARGET_LITTLE_ENDIAN)) { (target->endianness == TARGET_LITTLE_ENDIAN)) {
/* /*
* endianness changed after NAND controller probed * endianness changed after NAND controller probed
@ -701,26 +701,27 @@ static int validate_target_state(struct nand_device *nand)
static int do_data_output(struct nand_device *nand) static int do_data_output(struct nand_device *nand)
{ {
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv; struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
struct target *target = nand->target; struct target *target = nand->target;
int poll_result; int poll_result;
uint16_t ecc_status; uint16_t ecc_status;
switch (mx2_nf_info->fin) { switch (mxc_nf_info->fin) {
case MX2_NF_FIN_DATAOUT: case MXC_NF_FIN_DATAOUT:
/* /*
* start data output operation (set MX2_NF_BIT_OP_DONE==0) * start data output operation (set MXC_NF_BIT_OP_DONE==0)
*/ */
target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_DATAOUT_TYPE(mx2_nf_info->optype)); target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info->optype));
poll_result = poll_for_complete_op(target, "data output"); poll_result = poll_for_complete_op(target, "data output");
if (poll_result != ERROR_OK) if (poll_result != ERROR_OK)
return poll_result; return poll_result;
mx2_nf_info->fin = MX2_NF_FIN_NONE; mxc_nf_info->fin = MXC_NF_FIN_NONE;
/* /*
* ECC stuff * ECC stuff
*/ */
if ((mx2_nf_info->optype == MX2_NF_DATAOUT_PAGE) && mx2_nf_info->flags.hw_ecc_enabled) { if ((mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE) &&
target_read_u16(target, MX2_NF_ECCSTATUS, &ecc_status); mxc_nf_info->flags.hw_ecc_enabled) {
target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
switch (ecc_status & 0x000c) { switch (ecc_status & 0x000c) {
case 1 << 2: case 1 << 2:
LOG_INFO("main area readed with 1 (correctable) error"); LOG_INFO("main area readed with 1 (correctable) error");
@ -741,22 +742,22 @@ static int do_data_output(struct nand_device *nand)
} }
} }
break; break;
case MX2_NF_FIN_NONE: case MXC_NF_FIN_NONE:
break; break;
} }
return ERROR_OK; return ERROR_OK;
} }
struct nand_flash_controller imx27_nand_flash_controller = { struct nand_flash_controller mxc_nand_flash_controller = {
.name = "imx27", .name = "mxc",
.nand_device_command = &imx27_nand_device_command, .nand_device_command = &mxc_nand_device_command,
.init = &imx27_init, .init = &mxc_init,
.reset = &imx27_reset, .reset = &mxc_reset,
.command = &imx27_command, .command = &mxc_command,
.address = &imx27_address, .address = &mxc_address,
.write_data = &imx27_write_data, .write_data = &mxc_write_data,
.read_data = &imx27_read_data, .read_data = &mxc_read_data,
.write_page = &imx27_write_page, .write_page = &mxc_write_page,
.read_page = &imx27_read_page, .read_page = &mxc_read_page,
.nand_ready = &imx27_nand_ready, .nand_ready = &mxc_nand_ready,
}; };

120
src/flash/nand/mx2.h
View File

@ -21,88 +21,88 @@
***************************************************************************/ ***************************************************************************/
/* /*
* Freescale iMX2* OpenOCD NAND Flash controller support. * Freescale iMX OpenOCD NAND Flash controller support.
* based on Freescale iMX3* OpenOCD NAND Flash controller support. * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
* *
* Many thanks to Ben Dooks for writing s3c24xx driver. * Many thanks to Ben Dooks for writing s3c24xx driver.
*/ */
#define MX2_NF_BASE_ADDR 0xd8000000 #define MXC_NF_BASE_ADDR 0xd8000000
#define MX2_NF_BUFSIZ (MX2_NF_BASE_ADDR + 0xe00) #define MXC_NF_BUFSIZ (MXC_NF_BASE_ADDR + 0xe00)
#define MX2_NF_BUFADDR (MX2_NF_BASE_ADDR + 0xe04) #define MXC_NF_BUFADDR (MXC_NF_BASE_ADDR + 0xe04)
#define MX2_NF_FADDR (MX2_NF_BASE_ADDR + 0xe06) #define MXC_NF_FADDR (MXC_NF_BASE_ADDR + 0xe06)
#define MX2_NF_FCMD (MX2_NF_BASE_ADDR + 0xe08) #define MXC_NF_FCMD (MXC_NF_BASE_ADDR + 0xe08)
#define MX2_NF_BUFCFG (MX2_NF_BASE_ADDR + 0xe0a) #define MXC_NF_BUFCFG (MXC_NF_BASE_ADDR + 0xe0a)
#define MX2_NF_ECCSTATUS (MX2_NF_BASE_ADDR + 0xe0c) #define MXC_NF_ECCSTATUS (MXC_NF_BASE_ADDR + 0xe0c)
#define MX2_NF_ECCMAINPOS (MX2_NF_BASE_ADDR + 0xe0e) #define MXC_NF_ECCMAINPOS (MXC_NF_BASE_ADDR + 0xe0e)
#define MX2_NF_ECCSPAREPOS (MX2_NF_BASE_ADDR + 0xe10) #define MXC_NF_ECCSPAREPOS (MXC_NF_BASE_ADDR + 0xe10)
#define MX2_NF_FWP (MX2_NF_BASE_ADDR + 0xe12) #define MXC_NF_FWP (MXC_NF_BASE_ADDR + 0xe12)
#define MX2_NF_LOCKSTART (MX2_NF_BASE_ADDR + 0xe14) #define MXC_NF_LOCKSTART (MXC_NF_BASE_ADDR + 0xe14)
#define MX2_NF_LOCKEND (MX2_NF_BASE_ADDR + 0xe16) #define MXC_NF_LOCKEND (MXC_NF_BASE_ADDR + 0xe16)
#define MX2_NF_FWPSTATUS (MX2_NF_BASE_ADDR + 0xe18) #define MXC_NF_FWPSTATUS (MXC_NF_BASE_ADDR + 0xe18)
/* /*
* all bits not marked as self-clearing bit * all bits not marked as self-clearing bit
*/ */
#define MX2_NF_CFG1 (MX2_NF_BASE_ADDR + 0xe1a) #define MXC_NF_CFG1 (MXC_NF_BASE_ADDR + 0xe1a)
#define MX2_NF_CFG2 (MX2_NF_BASE_ADDR + 0xe1c) #define MXC_NF_CFG2 (MXC_NF_BASE_ADDR + 0xe1c)
#define MX2_NF_MAIN_BUFFER0 (MX2_NF_BASE_ADDR + 0x0000) #define MXC_NF_MAIN_BUFFER0 (MXC_NF_BASE_ADDR + 0x0000)
#define MX2_NF_MAIN_BUFFER1 (MX2_NF_BASE_ADDR + 0x0200) #define MXC_NF_MAIN_BUFFER1 (MXC_NF_BASE_ADDR + 0x0200)
#define MX2_NF_MAIN_BUFFER2 (MX2_NF_BASE_ADDR + 0x0400) #define MXC_NF_MAIN_BUFFER2 (MXC_NF_BASE_ADDR + 0x0400)
#define MX2_NF_MAIN_BUFFER3 (MX2_NF_BASE_ADDR + 0x0600) #define MXC_NF_MAIN_BUFFER3 (MXC_NF_BASE_ADDR + 0x0600)
#define MX2_NF_SPARE_BUFFER0 (MX2_NF_BASE_ADDR + 0x0800) #define MXC_NF_SPARE_BUFFER0 (MXC_NF_BASE_ADDR + 0x0800)
#define MX2_NF_SPARE_BUFFER1 (MX2_NF_BASE_ADDR + 0x0810) #define MXC_NF_SPARE_BUFFER1 (MXC_NF_BASE_ADDR + 0x0810)
#define MX2_NF_SPARE_BUFFER2 (MX2_NF_BASE_ADDR + 0x0820) #define MXC_NF_SPARE_BUFFER2 (MXC_NF_BASE_ADDR + 0x0820)
#define MX2_NF_SPARE_BUFFER3 (MX2_NF_BASE_ADDR + 0x0830) #define MXC_NF_SPARE_BUFFER3 (MXC_NF_BASE_ADDR + 0x0830)
#define MX2_NF_MAIN_BUFFER_LEN 512 #define MXC_NF_MAIN_BUFFER_LEN 512
#define MX2_NF_SPARE_BUFFER_LEN 16 #define MXC_NF_SPARE_BUFFER_LEN 16
#define MX2_NF_LAST_BUFFER_ADDR ((MX2_NF_SPARE_BUFFER3) + \ #define MXC_NF_LAST_BUFFER_ADDR ((MXC_NF_SPARE_BUFFER3) + \
MX2_NF_SPARE_BUFFER_LEN - 2) MXC_NF_SPARE_BUFFER_LEN - 2)
/* bits in MX2_NF_CFG1 register */ /* bits in MXC_NF_CFG1 register */
#define MX2_NF_BIT_SPARE_ONLY_EN (1<<2) #define MXC_NF_BIT_SPARE_ONLY_EN (1<<2)
#define MX2_NF_BIT_ECC_EN (1<<3) #define MXC_NF_BIT_ECC_EN (1<<3)
#define MX2_NF_BIT_INT_DIS (1<<4) #define MXC_NF_BIT_INT_DIS (1<<4)
#define MX2_NF_BIT_BE_EN (1<<5) #define MXC_NF_BIT_BE_EN (1<<5)
#define MX2_NF_BIT_RESET_EN (1<<6) #define MXC_NF_BIT_RESET_EN (1<<6)
#define MX2_NF_BIT_FORCE_CE (1<<7) #define MXC_NF_BIT_FORCE_CE (1<<7)
/* bits in MX2_NF_CFG2 register */ /* bits in MXC_NF_CFG2 register */
/*Flash Command Input*/ /*Flash Command Input*/
#define MX2_NF_BIT_OP_FCI (1<<0) #define MXC_NF_BIT_OP_FCI (1<<0)
/* /*
* Flash Address Input * Flash Address Input
*/ */
#define MX2_NF_BIT_OP_FAI (1<<1) #define MXC_NF_BIT_OP_FAI (1<<1)
/* /*
* Flash Data Input * Flash Data Input
*/ */
#define MX2_NF_BIT_OP_FDI (1<<2) #define MXC_NF_BIT_OP_FDI (1<<2)
/* see "enum mx_dataout_type" below */ /* see "enum mx_dataout_type" below */
#define MX2_NF_BIT_DATAOUT_TYPE(x) ((x)<<3) #define MXC_NF_BIT_DATAOUT_TYPE(x) ((x)<<3)
#define MX2_NF_BIT_OP_DONE (1<<15) #define MXC_NF_BIT_OP_DONE (1<<15)
#define MX2_CCM_CGR2 0x53f80028 #define MXC_CCM_CGR2 0x53f80028
#define MX2_GPR 0x43fac008 #define MXC_GPR 0x43fac008
/*#define MX2_PCSR 0x53f8000c*/ /*#define MXC_PCSR 0x53f8000c*/
#define MX2_FMCR 0x10027814 #define MXC_FMCR 0x10027814
#define MX2_FMCR_NF_16BIT_SEL (1<<4) #define MXC_FMCR_NF_16BIT_SEL (1<<4)
#define MX2_FMCR_NF_FMS (1<<5) #define MXC_FMCR_NF_FMS (1<<5)
enum mx_dataout_type { enum mxc_dataout_type {
MX2_NF_DATAOUT_PAGE = 1, MXC_NF_DATAOUT_PAGE = 1,
MX2_NF_DATAOUT_NANDID = 2, MXC_NF_DATAOUT_NANDID = 2,
MX2_NF_DATAOUT_NANDSTATUS = 4, MXC_NF_DATAOUT_NANDSTATUS = 4,
}; };
enum mx_nf_finalize_action { enum mxc_nf_finalize_action {
MX2_NF_FIN_NONE, MXC_NF_FIN_NONE,
MX2_NF_FIN_DATAOUT, MXC_NF_FIN_DATAOUT,
}; };
struct mx2_nf_flags { struct mxc_nf_flags {
unsigned host_little_endian:1; unsigned host_little_endian:1;
unsigned target_little_endian:1; unsigned target_little_endian:1;
unsigned nand_readonly:1; unsigned nand_readonly:1;
@ -110,8 +110,8 @@ struct mx2_nf_flags {
unsigned hw_ecc_enabled:1; unsigned hw_ecc_enabled:1;
}; };
struct mx2_nf_controller { struct mxc_nf_controller {
enum mx_dataout_type optype; enum mxc_dataout_type optype;
enum mx_nf_finalize_action fin; enum mxc_nf_finalize_action fin;
struct mx2_nf_flags flags; struct mxc_nf_flags flags;
}; };

2
tcl/board/tx27_stk5.cfg
View File

@ -61,4 +61,4 @@ proc tx27_init { } {
nand probe 0 nand probe 0
} }
nand device tx27.nand imx27 $_TARGETNAME hwecc nand device tx27.nand mxc $_TARGETNAME hwecc