Work in progress on arm11 reset. Assert srst.
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@ -1200,18 +1200,62 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl
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int arm11_assert_reset(target_t *target)
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int arm11_assert_reset(target_t *target)
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{
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{
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FNC_INFO;
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FNC_INFO;
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int retval;
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/* FIX! we really should assert srst here, but
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arm11_common_t * arm11 = target->arch_info;
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* how do we reset the target into the halted state?
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retval = arm11_check_init(arm11, NULL);
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*
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if (retval != ERROR_OK)
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* Also arm11 behaves "funny" when srst is asserted
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return retval;
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* (as of writing the rules are not understood).
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*/
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target->state = TARGET_UNKNOWN;
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/* we would very much like to reset into the halted, state,
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* but resetting and halting is second best... */
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if (target->reset_halt)
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if (target->reset_halt)
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{
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{
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CHECK_RETVAL(target_halt(target));
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CHECK_RETVAL(target_halt(target));
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}
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}
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/* srst is funny. We can not do *anything* else while it's asserted
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* and it has unkonwn side effects. Make sure no other code runs
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* meanwhile.
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*
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* Code below assumes srst:
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*
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* - Causes power-on-reset (but of what parts of the system?). Bug
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* in arm11?
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*
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* - Messes us TAP state without asserting trst.
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*
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* - There is another bug in the arm11 core. When you generate an access to
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* external logic (for example ddr controller via AHB bus) and that block
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* is not configured (perhaps it is still held in reset), that transaction
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* will never complete. This will hang arm11 core but it will also hang
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* JTAG controller. Nothing, short of srst assertion will bring it out of
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* this.
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*
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* Mysteries:
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*
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* - What should the PC be after an srst reset when starting in the halted
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* state?
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*/
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jtag_add_reset(0, 1);
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jtag_add_reset(0, 0);
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/* How long do we have to wait? */
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jtag_add_sleep(5000);
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/* un-mess up TAP state */
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jtag_add_tlr();
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retval = jtag_execute_queue();
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if (retval != ERROR_OK)
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{
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return retval;
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}
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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