Michael Hasselberg <mh@open-engineering.de> target configuration files for Toshiba TX09 familiy
git-svn-id: svn://svn.berlios.de/openocd/trunk@2756 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe
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1c262c8826
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43b3807878
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######################################
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# Target: Toshiba TOPAS910 -- TMPA910 Starterkit
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#
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######################################
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# We add to the minimal configuration.
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source [find target/tmpa910.cfg]
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######################
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# Target configuration
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######################
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#$_TARGETNAME configure -event gdb-attach { reset init }
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$_TARGETNAME configure -event reset-init { topas910_init }
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proc topas910_init { } {
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# Init PLL
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# my settings
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mww 0xf005000c 0x00000007
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mww 0xf0050010 0x00000065
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mww 0xf005000c 0x000000a7
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sleep 10
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mdw 0xf0050008
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mww 0xf0050008 0x00000002
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mww 0xf0050004 0x00000000
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# NEW: set CLKCR5
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mww 0xf0050054 0x00000040
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#
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sleep 10
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# Init SDRAM
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# _PMCDRV = 0x00000071;
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# //
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# // Initialize SDRAM timing paramater
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# //
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# _DMC_CAS_LATENCY = 0x00000006;
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# _DMC_T_DQSS = 0x00000000;
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# _DMC_T_MRD = 0x00000002;
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# _DMC_T_RAS = 0x00000007;
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#
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# _DMC_T_RC = 0x0000000A;
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# _DMC_T_RCD = 0x00000013;
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#
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# _DMC_T_RFC = 0x0000010A;
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#
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# _DMC_T_RP = 0x00000013;
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# _DMC_T_RRD = 0x00000002;
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# _DMC_T_WR = 0x00000002;
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# _DMC_T_WTR = 0x00000001;
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# _DMC_T_XP = 0x0000000A;
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# _DMC_T_XSR = 0x0000000B;
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# _DMC_T_ESR = 0x00000014;
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#
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# //
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# // Configure SDRAM type parameter
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# _DMC_MEMORY_CFG = 0x00008011;
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# _DMC_USER_CONFIG = 0x00000011;
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# // 32 bit memory interface
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#
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#
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# _DMC_REFRESH_PRD = 0x00000A60;
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# _DMC_CHIP_0_CFG = 0x000140FC;
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#
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# _DMC_DIRECT_CMD = 0x000C0000;
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# _DMC_DIRECT_CMD = 0x00000000;
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#
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# _DMC_DIRECT_CMD = 0x00040000;
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# _DMC_DIRECT_CMD = 0x00040000;
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# _DMC_DIRECT_CMD = 0x00080031;
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# //
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# // Finally start SDRAM
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# //
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# _DMC_MEMC_CMD = MEMC_CMD_GO;
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# */
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mww 0xf0020260 0x00000071
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mww 0xf4300014 0x00000006
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mww 0xf4300018 0x00000000
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mww 0xf430001C 0x00000002
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mww 0xf4300020 0x00000007
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mww 0xf4300024 0x0000000A
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mww 0xf4300028 0x00000013
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mww 0xf430002C 0x0000010A
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mww 0xf4300030 0x00000013
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mww 0xf4300034 0x00000002
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mww 0xf4300038 0x00000002
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mww 0xf430003C 0x00000001
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mww 0xf4300040 0x0000000A
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mww 0xf4300044 0x0000000B
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mww 0xf4300048 0x00000014
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mww 0xf430000C 0x00008011
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mww 0xf4300304 0x00000011
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mww 0xf4300010 0x00000A60
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mww 0xf4300200 0x000140FC
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mww 0xf4300008 0x000C0000
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mww 0xf4300008 0x00000000
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mww 0xf4300008 0x00040000
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mww 0xf4300008 0x00040000
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mww 0xf4300008 0x00080031
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mww 0xf4300004 0x00000000
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sleep 10
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# jtag_speed 10000
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# remap off in case of IROM boot
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mww 0xf0000004 0x00000001
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}
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# comment the following out if usinf J-Link, it soes not support DCC
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arm7_9 dcc_downloads enable # Enable faster DCC downloads
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#####################
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# Flash configuration
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#####################
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#flash bank cfi <base> <size> <chip width> <bus width> <target#>
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flash bank cfi 0x20000000 0x2000000 2 2 0
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@ -0,0 +1,125 @@
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# Thanks to Pieter Conradie for this script!
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# Target: Toshiba TOPAS900 -- TMPA900 Starterkit
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######################################
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# We add to the minimal configuration.
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source [find target/tmpa900.cfg]
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######################
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# Target configuration
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######################
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#$_TARGETNAME configure -event gdb-attach { reset init }
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$_TARGETNAME configure -event reset-init { topasa900_init }
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proc topasa900_init { } {
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# Init PLL
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# my settings
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mww 0xf005000c 0x00000007
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mww 0xf0050010 0x00000065
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mww 0xf005000c 0x000000a7
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sleep 10
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mdw 0xf0050008
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mww 0xf0050008 0x00000002
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mww 0xf0050004 0x00000000
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# NEW: set CLKCR5
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mww 0xf0050054 0x00000040
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#
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# bplan settings
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# mww 0xf0050004 0x00000000
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# mww 0xf005000c 0x000000a7
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# sleep 10
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# mdw 0xf0050008
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# mww 0xf0050008 0x00000002
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# mww 0xf0050010 0x00000065
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# mww 0xf0050054 0x00000040
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sleep 10
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# Init SDRAM
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# _PMCDRV = 0x00000071;
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# //
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# // Initialize SDRAM timing paramater
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# //
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# _DMC_CAS_LATENCY = 0x00000006;
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# _DMC_T_DQSS = 0x00000000;
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# _DMC_T_MRD = 0x00000002;
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# _DMC_T_RAS = 0x00000007;
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#
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# _DMC_T_RC = 0x0000000A;
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# _DMC_T_RCD = 0x00000013;
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#
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# _DMC_T_RFC = 0x0000010A;
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#
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# _DMC_T_RP = 0x00000013;
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# _DMC_T_RRD = 0x00000002;
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# _DMC_T_WR = 0x00000002;
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# _DMC_T_WTR = 0x00000001;
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# _DMC_T_XP = 0x0000000A;
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# _DMC_T_XSR = 0x0000000B;
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# _DMC_T_ESR = 0x00000014;
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#
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# //
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# // Configure SDRAM type parameter
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# _DMC_MEMORY_CFG = 0x00008011;
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# _DMC_USER_CONFIG = 0x00000011; // 32 bit memory interface
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#
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#
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# _DMC_REFRESH_PRD = 0x00000A60;
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# _DMC_CHIP_0_CFG = 0x000140FC;
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#
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# _DMC_DIRECT_CMD = 0x000C0000;
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# _DMC_DIRECT_CMD = 0x00000000;
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#
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# _DMC_DIRECT_CMD = 0x00040000;
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# _DMC_DIRECT_CMD = 0x00040000;
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# _DMC_DIRECT_CMD = 0x00080031;
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# //
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# // Finally start SDRAM
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# //
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# _DMC_MEMC_CMD = MEMC_CMD_GO;
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# */
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mww 0xf0020260 0x00000071
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mww 0xf4300014 0x00000006
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mww 0xf4300018 0x00000000
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mww 0xf430001C 0x00000002
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mww 0xf4300020 0x00000007
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mww 0xf4300024 0x0000000A
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mww 0xf4300028 0x00000013
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mww 0xf430002C 0x0000010A
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mww 0xf4300030 0x00000013
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mww 0xf4300034 0x00000002
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mww 0xf4300038 0x00000002
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mww 0xf430003C 0x00000001
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mww 0xf4300040 0x0000000A
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mww 0xf4300044 0x0000000B
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mww 0xf4300048 0x00000014
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mww 0xf430000C 0x00008011
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mww 0xf4300304 0x00000011
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mww 0xf4300010 0x00000A60
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mww 0xf4300200 0x000140FC
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mww 0xf4300008 0x000C0000
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mww 0xf4300008 0x00000000
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mww 0xf4300008 0x00040000
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mww 0xf4300008 0x00040000
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mww 0xf4300008 0x00080031
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mww 0xf4300004 0x00000000
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sleep 10
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# jtag_speed 10000
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# remap off in case of IROM boot
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mww 0xf0000004 0x00000001
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}
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# comment the following out if usinf J-Link, it soes not support DCC
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arm7_9 dcc_downloads enable # Enable faster DCC downloads
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#####################
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# Flash configuration
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#####################
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#flash bank cfi <base> <size> <chip width> <bus width> <target#>
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flash bank cfi 0x20000000 0x1000000 2 2 0
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@ -0,0 +1,56 @@
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######################################
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# Target: Toshiba TMPA910
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######################################
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME tmpa910
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# force an error till we get a good number
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set _CPUTAPID 0x07926031
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}
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#TMPA910 has following IDs:
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# CP15.0 register 0x41069265
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# CP15.1 register 0x1d152152
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# ARM core 0x07926031
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#
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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#use combined on interfaces or targets that can't set TRST/SRST separately
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reset_config trst_and_srst
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jtag_nsrst_delay 20
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jtag_ntrst_delay 20
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######################
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# Target configuration
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######################
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set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
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target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
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# built-in RAM0
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#working_area 0 0xf8004000 0x4000 nobackup
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# built-in RAM1
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#working_area 1 0xf8008000 0x4000 nobackup
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# built-in RAM2
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#working_area 2 0xf800c000 0x4000 nobackup
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# built-in RAM 0-2 48k total
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#working_area 0 0xf8004000 0xc000 nobackup
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# Internal sram1 memory
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$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0xf8004000 -work-area-size 0x8000 \
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-work-area-backup 0
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######################################
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# Target: Toshiba TMPA910
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######################################
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME tmpa910
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# force an error till we get a good number
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set _CPUTAPID 0x07926031
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}
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#TMPA910 has following IDs:
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# CP15.0 register 0x41069265
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# CP15.1 register 0x1d152152
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# ARM core 0x07926031
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#
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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#use combined on interfaces or targets that can't set TRST/SRST separately
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reset_config trst_and_srst
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jtag_nsrst_delay 20
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jtag_ntrst_delay 20
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######################
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# Target configuration
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######################
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set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
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target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
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# built-in RAM0
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#working_area 0 0xf8004000 0x4000 nobackup
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# built-in RAM1
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#working_area 1 0xf8008000 0x4000 nobackup
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# built-in RAM2
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#working_area 2 0xf800c000 0x4000 nobackup
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# built-in RAM 0-2 48k total
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#working_area 0 0xf8004000 0xc000 nobackup
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# Internal sram1 memory
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$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0xf8004000 -work-area-size 0xc000 \
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-work-area-backup 0
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