interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

aarch64: correct breakpoint register offset 

armv8 breakpoint register spacing is 16, not 4 as in armv7-a

Change-Id: I0d49d06878a0c9dab35cde478064e5366f01a8e0
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
This commit is contained in:
Matthias Welwarsky 2016-09-16 15:16:19 +02:00
parent 4314624669
commit 42574b3a10
1 changed files with 4 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/target/aarch64.c
View File

@ -690,8 +690,8 @@ static int aarch64_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
default:
return ERROR_FAIL;
}
vr += 4 * index_t;
cr += 4 * index_t;
vr += 16 * index_t;
cr += 16 * index_t;
LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
(unsigned) vr, (unsigned) cr);
@ -707,9 +707,6 @@ static int aarch64_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
static int aarch64_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
{
return ERROR_OK;
#if 0
struct aarch64_common *a = dpm_to_a8(dpm);
uint32_t cr;
@ -724,13 +721,13 @@ static int aarch64_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
default:
return ERROR_FAIL;
}
cr += 4 * index_t;
cr += 16 * index_t;
LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
/* clear control register */
return aarch64_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
#endif
}
static int aarch64_dpm_setup(struct aarch64_common *a8, uint32_t debug)