From 42259dc9fb774fd2a29257d9808cc3decc07f8c5 Mon Sep 17 00:00:00 2001 From: Evgeniy Naydanov Date: Mon, 13 Jan 2025 17:33:38 +0300 Subject: [PATCH] target/riscv: drop `mtopi_readable/mtopei_readable` `riscv_info` fields These fields duplicate the info in the corresponding register cache entries. Change-Id: Ic0d264e78c527e92bb069258ce39b614d8f5bcde Signed-off-by: Evgeniy Naydanov --- src/target/riscv/riscv-011_reg.c | 4 ---- src/target/riscv/riscv-013_reg.c | 27 +++++++++--------------- src/target/riscv/riscv.h | 7 +++---- src/target/riscv/riscv_reg.c | 35 +++++++++++--------------------- 4 files changed, 25 insertions(+), 48 deletions(-) diff --git a/src/target/riscv/riscv-011_reg.c b/src/target/riscv/riscv-011_reg.c index f3f03dd96..3704880d1 100644 --- a/src/target/riscv/riscv-011_reg.c +++ b/src/target/riscv/riscv-011_reg.c @@ -48,10 +48,6 @@ int riscv011_reg_init_all(struct target *target) RISCV_INFO(r); assert(!r->vlenb && "VLENB discovery is not supported on RISC-V 0.11 targets"); - assert(!r->mtopi_readable - && "MTOPI discovery is not supported on RISC-V 0.11 targets"); - assert(!r->mtopei_readable - && "MTOPEI discovery is not supported on RISC-V 0.11 targets"); uint32_t non_discoverable_regs[] = { GDB_REGNO_VLENB, GDB_REGNO_MTOPI, diff --git a/src/target/riscv/riscv-013_reg.c b/src/target/riscv/riscv-013_reg.c index 514103b2d..b2b1a921f 100644 --- a/src/target/riscv/riscv-013_reg.c +++ b/src/target/riscv/riscv-013_reg.c @@ -266,12 +266,7 @@ static int examine_misa(struct target *target) static int examine_mtopi(struct target *target) { - RISCV_INFO(r); - /* Assume the registers exist */ - r->mtopi_readable = true; - r->mtopei_readable = true; - int res = assume_reg_exist(target, GDB_REGNO_MTOPI); if (res != ERROR_OK) return res; @@ -281,19 +276,17 @@ static int examine_mtopi(struct target *target) riscv_reg_t value; if (riscv_reg_get(target, &value, GDB_REGNO_MTOPI) != ERROR_OK) { - r->mtopi_readable = false; - r->mtopei_readable = false; - } else if (riscv_reg_get(target, &value, GDB_REGNO_MTOPEI) != ERROR_OK) { - LOG_TARGET_INFO(target, "S?aia detected without IMSIC"); - r->mtopei_readable = false; - } else { - LOG_TARGET_INFO(target, "S?aia detected with IMSIC"); + res = riscv_reg_impl_set_exist(target, GDB_REGNO_MTOPI, false); + if (res != ERROR_OK) + return res; + return riscv_reg_impl_set_exist(target, GDB_REGNO_MTOPEI, false); } - res = riscv_reg_impl_set_exist(target, GDB_REGNO_MTOPI, r->mtopi_readable); - if (res != ERROR_OK) - return res; - - return riscv_reg_impl_set_exist(target, GDB_REGNO_MTOPEI, r->mtopei_readable); + if (riscv_reg_get(target, &value, GDB_REGNO_MTOPEI) != ERROR_OK) { + LOG_TARGET_INFO(target, "S?aia detected without IMSIC"); + return riscv_reg_impl_set_exist(target, GDB_REGNO_MTOPEI, false); + } + LOG_TARGET_INFO(target, "S?aia detected with IMSIC"); + return ERROR_OK; } /** diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 482d0fd71..8437a69e8 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -175,15 +175,14 @@ struct riscv_info { /* It's possible that each core has a different supported ISA set. */ int xlen; + /* TODO: use the value from the register cache instead. */ riscv_reg_t misa; - /* Cached value of vlenb. 0 indicates there is no vector support. + /* TODO: use the value from the register cache instead. + * Cached value of vlenb. 0 indicates there is no vector support. * Note that you can have vector support without misa.V set, because * Zve* extensions implement vector registers without setting misa.V. */ unsigned int vlenb; - bool mtopi_readable; - bool mtopei_readable; - /* The number of triggers per hart. */ unsigned int trigger_count; diff --git a/src/target/riscv/riscv_reg.c b/src/target/riscv/riscv_reg.c index 29d8a2b65..a7d8f8268 100644 --- a/src/target/riscv/riscv_reg.c +++ b/src/target/riscv/riscv_reg.c @@ -346,22 +346,11 @@ static bool vlenb_exists(const struct target *target) return riscv_vlenb(target) != 0; } -static bool mtopi_exists(const struct target *target) +static bool query_reg_exist(const struct target *target, uint32_t regno) { - RISCV_INFO(info) - /* TODO: The naming is quite unfortunate here. `mtopi_readable` refers - * to how the fact that `mtopi` exists was deduced during examine. - */ - return info->mtopi_readable; -} - -static bool mtopei_exists(const struct target *target) -{ - RISCV_INFO(info) - /* TODO: The naming is quite unfortunate here. `mtopei_readable` refers - * to how the fact that `mtopei` exists was deduced during examine. - */ - return info->mtopei_readable; + const struct reg * const reg = riscv_reg_impl_cache_entry(target, regno); + assert(riscv_reg_impl_is_initialized(reg)); + return reg->exist; } static bool is_known_standard_csr(unsigned int csr_num) @@ -508,25 +497,25 @@ bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno) case CSR_MVIP: case CSR_MIEH: case CSR_MIPH: - return mtopi_exists(target); + return query_reg_exist(target, GDB_REGNO_MTOPI); case CSR_MIDELEGH: case CSR_MVIENH: case CSR_MVIPH: - return mtopi_exists(target) && + return query_reg_exist(target, GDB_REGNO_MTOPI) && riscv_xlen(target) == 32 && riscv_supports_extension(target, 'S'); /* Interrupts S-Mode CSRs. */ case CSR_SISELECT: case CSR_SIREG: case CSR_STOPI: - return mtopi_exists(target) && + return query_reg_exist(target, GDB_REGNO_MTOPI) && riscv_supports_extension(target, 'S'); case CSR_STOPEI: - return mtopei_exists(target) && + return query_reg_exist(target, GDB_REGNO_MTOPEI) && riscv_supports_extension(target, 'S'); case CSR_SIEH: case CSR_SIPH: - return mtopi_exists(target) && + return query_reg_exist(target, GDB_REGNO_MTOPI) && riscv_xlen(target) == 32 && riscv_supports_extension(target, 'S'); /* Interrupts Hypervisor and VS CSRs. */ @@ -537,10 +526,10 @@ bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno) case CSR_VSISELECT: case CSR_VSIREG: case CSR_VSTOPI: - return mtopi_exists(target) && + return query_reg_exist(target, GDB_REGNO_MTOPI) && riscv_supports_extension(target, 'H'); case CSR_VSTOPEI: - return mtopei_exists(target) && + return query_reg_exist(target, GDB_REGNO_MTOPEI) && riscv_supports_extension(target, 'H'); case CSR_HIDELEGH: case CSR_HVIENH: @@ -549,7 +538,7 @@ bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno) case CSR_HVIPRIO2H: case CSR_VSIEH: case CSR_VSIPH: - return mtopi_exists(target) && + return query_reg_exist(target, GDB_REGNO_MTOPI) && riscv_xlen(target) == 32 && riscv_supports_extension(target, 'H'); }