tcl/target/renesas_rz_g2: Rename to renesas_rz and add RZ/V2L-G3S
Rename file to get it more generic and add more targets belonging to the same family. Add support for two new devices: RZ/V2L and RZ/G3S Change-Id: Idb7f4d81d2f95ad15ef686e940f43ed29f49f343 Signed-off-by: MicBiso <michele.bisogno.ct@renesas.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8211 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
This commit is contained in:
MicBiso
Antonio Borneo
parent
3b261fb155
commit
40d58ce529
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@ -1,23 +1,25 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Renesas RZ/G2 SOCs
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# Renesas RZ SOCs
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# - There are a combination of Cortex-A57s, Cortex-A53s, Cortex-A55, Cortex-R7
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# and Cortex-M33 for each SOC
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# - Each SOC can boot through the Cortex-A5x cores
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# - Each SOC can boot through the Cortex-A5x cores or the Cortex-M33
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# Supported RZ/G2 SOCs and their cores:
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# Supported RZ SOCs and their cores:
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# RZ/G2H: Cortex-A57 x4, Cortex-A53 x4, Cortex-R7
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# RZ/G2M: Cortex-A57 x2, Cortex-A53 x4, Cortex-R7
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# RZ/G2N: Cortex-A57 x2, Cortex-R7
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# RZ/G2E: Cortex-A53 x2, Cortex-R7
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# RZ/G2L: Cortex-A55 x2, Cortex-M33
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# RZ/V2L: Cortex-A55 x2, Cortex-M33
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# RZ/G2LC: Cortex-A55 x2, Cortex-M33
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# RZ/G2UL: Cortex-A55 x1, Cortex-M33
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# RZ/G3S: Cortex-A55 x1, Cortex-M33 x2
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# Usage:
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# There are 2 configuration options:
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# SOC: Selects the supported SOC. (Default 'G2L')
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# BOOT_CORE: Selects the booting core. 'CA57', 'CA53' or 'CA55'
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# BOOT_CORE: Selects the booting core. 'CA57', 'CA53', 'CA55' or CM33
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transport select jtag
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reset_config trst_and_srst srst_gates_jtag
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@ -77,6 +79,13 @@ switch $_soc {
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set _boot_core CA55
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set _ap_num 0
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}
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V2L {
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set _CHIPNAME r9a07g054l
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set _num_ca55 2
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set _num_cm33 1
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set _boot_core CA55
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set _ap_num 0
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}
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G2LC {
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set _CHIPNAME r9a07g044c
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set _num_ca55 2
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@ -91,6 +100,13 @@ switch $_soc {
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set _boot_core CA55
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set _ap_num 0
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}
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G3S {
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set _CHIPNAME r9a08g045s
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set _num_ca55 1
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set _num_cm33 2
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set _boot_core CA55
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set _ap_num 0
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}
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default {
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error "'$_soc' is invalid!"
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}
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@ -112,16 +128,16 @@ if { [info exists DAP_TAPID] } {
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set _DAP_TAPID 0x6ba00477
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}
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echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca55 CA55(s), $_num_ca53 CA53(s), $_num_cr7 CR7(s), \
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$_num_cm33 CM33(s)"
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echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca55 CA55(s), $_num_ca53 CA53(s), \
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$_num_cr7 CR7(s), $_num_cm33 CM33(s)"
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echo "\tBoot Core - $_boot_core\n"
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set _DAPNAME $_CHIPNAME.dap
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# TAP and DAP
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID \
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-ignore-version
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_DAP_TAPID -ignore-version
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dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
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echo "$_CHIPNAME.cpu"
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@ -133,8 +149,8 @@ set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000}
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set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000}
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set CR7_DBGBASE 0x80910000
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set CR7_CTIBASE 0x80918000
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set CM33_DBGBASE 0xE000E000
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set CM33_CTIBASE 0xE0042000
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set CM33_DBGBASE {0xE000E000 0xE010E000}
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set CM33_CTIBASE {0xE0042000 0xE0142000}
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set smp_targets ""
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@ -145,7 +161,8 @@ proc setup_a5x {core_name dbgbase ctibase num boot} {
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cti create $_CTINAME -dap $::_DAPNAME -ap-num $::_ap_num \
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-baseaddr [lindex $ctibase $_core]
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target create $_TARGETNAME aarch64 -dap $::_DAPNAME \
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-ap-num $::_ap_num -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME
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-ap-num $::_ap_num -dbgbase [lindex $dbgbase $_core] \
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-cti $_CTINAME
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if { $_core > 0 || $boot == 0 } {
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$_TARGETNAME configure -defer-examine
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}
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@ -160,13 +177,29 @@ proc setup_cr7 {dbgbase ctibase} {
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target create $_TARGETNAME cortex_r4 -dap $::_DAPNAME \
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-ap-num 1 -dbgbase $dbgbase -defer-examine
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}
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proc setup_cm33 {dbgbase ctibase} {
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set _TARGETNAME $::_CHIPNAME.m33
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set _CTINAME $_TARGETNAME.cti
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cti create $_CTINAME -dap $::_DAPNAME -ap-num 2 -baseaddr $ctibase
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target create $_TARGETNAME cortex_m -dap $::_DAPNAME \
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-ap-num 2 -dbgbase $dbgbase -defer-examine
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proc setup_cm33 {dbgbase ctibase num boot} {
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if { $::_soc == "G2L" || $::_soc == "V2L" \
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|| $::_soc == "G2LC" || $::_soc == "G2UL" } {
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set _ap_num 2
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} elseif { $::_soc == "G3S" } {
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set _ap_num 3
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}
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for { set _core 0 } { $_core < $num } { incr _core } {
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if { $num <= 1 } {
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set _TARGETNAME $::_CHIPNAME.m33
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} else {
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set _TARGETNAME $::_CHIPNAME.m33.$_core
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}
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set _CTINAME $_TARGETNAME.cti
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cti create $_CTINAME -dap $::_DAPNAME -ap-num $_ap_num \
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-baseaddr [lindex $ctibase $_core]
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target create $_TARGETNAME cortex_m -dap $::_DAPNAME \
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-ap-num $_ap_num -dbgbase [lindex $dbgbase $_core]
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if { $boot == 0 } {
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$_TARGETNAME configure -defer-examine
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}
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incr $_ap_num
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}
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}
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# Organize target list based on the boot core
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@ -180,12 +213,17 @@ if { $_boot_core == "CA57" } {
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setup_cr7 $CR7_DBGBASE $CR7_CTIBASE
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} elseif { $_boot_core == "CA55" } {
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setup_a5x a55 $CA55_DBGBASE $CA55_CTIBASE $_num_ca55 1
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setup_cm33 $CM33_DBGBASE $CM33_CTIBASE
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setup_cm33 $CM33_DBGBASE $CM33_CTIBASE $_num_cm33 0
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} elseif { $_boot_core == "CM33" } {
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setup_a5x a55 $CA55_DBGBASE $CA55_CTIBASE $_num_ca55 0
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setup_cm33 $CM33_DBGBASE $CM33_CTIBASE $_num_cm33 1
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}
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echo "SMP targets:$smp_targets"
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eval "target smp $smp_targets"
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if { $_soc == "G2L" || $_soc == "G2LC" || $_soc == "G2UL" } {
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if { $_soc == "G2L" || $_soc == "V2L" || $_soc == "G2LC" \
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|| $_soc == "G2UL" || $_soc == "G3S"} {
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target create $_CHIPNAME.axi_ap mem_ap -dap $_DAPNAME -ap-num 1
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}
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