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riscv-openocd
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Merge remote-tracking branch 'origin/riscv' into HEAD

This commit is contained in:
Megan Wachs 2018-04-18 15:22:38 -07:00
parent 8fa81c1f97 69a426038d
commit 3fedb7d97f
4 changed files with 16 additions and 18 deletions
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8
.travis.yml
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@ -50,7 +50,11 @@ matrix:
- binutils-mingw-w64-i686 gcc-mingw-w64-i686 g++-mingw-w64-i686 - binutils-mingw-w64-i686 gcc-mingw-w64-i686 g++-mingw-w64-i686
script: script:
- set -o pipefail # Ideally we'd diff back to where we either branched off OpenOCD or master,
- git diff `git merge-base master HEAD` | ./tools/scripts/checkpatch.pl - # or riscv. But that's tricky, and the default git clone only gets the last
# 50 changes any case. Most merges won't consist of more than 40 changes,
# so this should work fine most of the time, and be a lot better than not
# checking at all.
- git diff HEAD~40 | ./tools/scripts/checkpatch.pl --no-signoff -
- ./bootstrap && ./configure --enable-remote-bitbang --enable-jtag_vpi $CONFIGURE_ARGS && make - ./bootstrap && ./configure --enable-remote-bitbang --enable-jtag_vpi $CONFIGURE_ARGS && make
- file src/$EXECUTABLE - file src/$EXECUTABLE

6
src/target/riscv/riscv-011.c
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@ -455,12 +455,12 @@ static uint64_t dbus_read(struct target *target, uint16_t address)
uint64_t value; uint64_t value;
dbus_status_t status; dbus_status_t status;
uint16_t address_in; uint16_t address_in;
/* If the previous read/write was to the same address, we will get the read data /* If the previous read/write was to the same address, we will get the read data
* from the previous access. * from the previous access.
* While somewhat nonintuitive, this is an efficient way to get the data. * While somewhat nonintuitive, this is an efficient way to get the data.
*/ */
unsigned i = 0; unsigned i = 0;
do { do {
status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, address, 0); status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, address, 0);
@ -680,7 +680,7 @@ static bits_t read_bits(struct target *target)
} }
increase_dbus_busy_delay(target); increase_dbus_busy_delay(target);
} else if (status == DBUS_STATUS_FAILED) { } else if (status == DBUS_STATUS_FAILED) {
// TODO: return an actual error /* TODO: return an actual error */
return err_result; return err_result;
} }
} while (status == DBUS_STATUS_BUSY && i++ < 256); } while (status == DBUS_STATUS_BUSY && i++ < 256);

12
src/target/riscv/riscv-013.c
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@ -250,9 +250,8 @@ static dm013_info_t *get_dm(struct target *target)
info->dm = dm; info->dm = dm;
target_list_t *target_entry; target_list_t *target_entry;
list_for_each_entry(target_entry, &dm->target_list, list) { list_for_each_entry(target_entry, &dm->target_list, list) {
if (target_entry->target == target) { if (target_entry->target == target)
return dm; return dm;
}
} }
target_entry = calloc(1, sizeof(*target_entry)); target_entry = calloc(1, sizeof(*target_entry));
target_entry->target = target; target_entry->target = target;
@ -1781,19 +1780,16 @@ static int sb_write_address(struct target *target, target_addr_t address)
RISCV013_INFO(info); RISCV013_INFO(info);
unsigned sbasize = get_field(info->sbcs, DMI_SBCS_SBASIZE); unsigned sbasize = get_field(info->sbcs, DMI_SBCS_SBASIZE);
/* There currently is no support for >64-bit addresses in OpenOCD. */ /* There currently is no support for >64-bit addresses in OpenOCD. */
if (sbasize > 96) { if (sbasize > 96)
dmi_write(target, DMI_SBADDRESS3, 0); dmi_write(target, DMI_SBADDRESS3, 0);
} if (sbasize > 64)
if (sbasize > 64) {
dmi_write(target, DMI_SBADDRESS2, 0); dmi_write(target, DMI_SBADDRESS2, 0);
} if (sbasize > 32)
if (sbasize > 32) {
#if BUILD_TARGET64 #if BUILD_TARGET64
dmi_write(target, DMI_SBADDRESS1, address >> 32); dmi_write(target, DMI_SBADDRESS1, address >> 32);
#else #else
dmi_write(target, DMI_SBADDRESS1, 0); dmi_write(target, DMI_SBADDRESS1, 0);
#endif #endif
}
return dmi_write(target, DMI_SBADDRESS0, address); return dmi_write(target, DMI_SBADDRESS0, address);
} }

8
src/target/riscv/riscv.c
View File

@ -1125,16 +1125,14 @@ int riscv_openocd_resume(
while (watchpoint && result == ERROR_OK) { while (watchpoint && result == ERROR_OK) {
LOG_DEBUG("watchpoint %d: set=%d", i, watchpoint->set); LOG_DEBUG("watchpoint %d: set=%d", i, watchpoint->set);
trigger_temporarily_cleared[i] = watchpoint->set; trigger_temporarily_cleared[i] = watchpoint->set;
if (watchpoint->set) { if (watchpoint->set)
result = riscv_remove_watchpoint(target, watchpoint); result = riscv_remove_watchpoint(target, watchpoint);
}
watchpoint = watchpoint->next; watchpoint = watchpoint->next;
i++; i++;
} }
if (result == ERROR_OK) { if (result == ERROR_OK)
result = riscv_step_rtos_hart(target); result = riscv_step_rtos_hart(target);
}
watchpoint = target->watchpoints; watchpoint = target->watchpoints;
i = 0; i = 0;
@ -1256,7 +1254,7 @@ COMMAND_HANDLER(riscv_set_scratch_ram)
return ERROR_OK; return ERROR_OK;
} }
/** TODO: use COMMAND_PARSE_NUMBER **/ /* TODO: use COMMAND_PARSE_NUMBER */
long long unsigned int address; long long unsigned int address;
int result = sscanf(CMD_ARGV[0], "%llx", &address); int result = sscanf(CMD_ARGV[0], "%llx", &address);
if (result != (int) strlen(CMD_ARGV[0])) { if (result != (int) strlen(CMD_ARGV[0])) {