interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

target/riscv: avoid unnecessary `dcsr.ebreak*` update on reset 

There is no need to change if `dcsr.ebreak*` fields after a reset if a
user requested a configuration that will result `dcsr.ebreak*` field
values equal to reset values.

Change-Id: I2844d30aef8f735c7b37394ee422e9b3f04a2e3b
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This commit is contained in:
Evgeniy Naydanov 2024-10-22 14:06:45 +03:00
parent 7b4ad6f173
commit 3fe20e7aa4
1 changed files with 7 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/target/riscv/riscv-013.c
View File

@ -2837,6 +2837,12 @@ static int assert_reset(struct target *target)
return riscv013_invalidate_cached_progbuf(target); return riscv013_invalidate_cached_progbuf(target);
} }
static bool dcsr_ebreak_config_equals_reset_value(const struct target *target)
{
RISCV_INFO(r);
return !(r->riscv_ebreakm || r->riscv_ebreaks || r->riscv_ebreaku);
}
static int deassert_reset(struct target *target) static int deassert_reset(struct target *target)
{ {
RISCV013_INFO(info); RISCV013_INFO(info);
@ -2903,7 +2909,7 @@ static int deassert_reset(struct target *target)
target->state = TARGET_RUNNING; target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED; target->debug_reason = DBG_REASON_NOTHALTED;
} }
info->dcsr_ebreak_is_set = false; info->dcsr_ebreak_is_set = dcsr_ebreak_config_equals_reset_value(target);
/* Ack reset and clear DM_DMCONTROL_HALTREQ if previously set */ /* Ack reset and clear DM_DMCONTROL_HALTREQ if previously set */
control = 0; control = 0;