interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Make CLI step and resume work. 

Change-Id: I027d7032800f909e8d149ed84c11b6e75b75491f
This commit is contained in:
Tim Newsome 2016-10-20 14:49:23 -07:00
parent 9b0be80d1e
commit 3eb6cf0fc0
1 changed files with 26 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

50
src/target/riscv/riscv.c
View File

@ -1079,7 +1079,7 @@ static int execute_resume(struct target *target, bool step)
{ {
riscv_info_t *info = (riscv_info_t *) target->arch_info; riscv_info_t *info = (riscv_info_t *) target->arch_info;
LOG_DEBUG("resume(step=%d)", step); LOG_DEBUG("step=%d", step);
maybe_write_tselect(target); maybe_write_tselect(target);
@ -1145,25 +1145,8 @@ static int full_step(struct target *target, bool announce)
return ERROR_OK; return ERROR_OK;
} }
static int resume(struct target *target, int current, uint32_t address, static int resume(struct target *target, int debug_execution, bool step)
int handle_breakpoints, int debug_execution, bool step)
{ {
riscv_info_t *info = (riscv_info_t *) target->arch_info;
if (!current) {
if (info->xlen > 32) {
LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
info->xlen);
}
LOG_ERROR("TODO: current is false");
return ERROR_FAIL;
}
if (handle_breakpoints) {
LOG_ERROR("TODO: handle_breakpoints is true");
return ERROR_FAIL;
}
if (debug_execution) { if (debug_execution) {
LOG_ERROR("TODO: debug_execution is true"); LOG_ERROR("TODO: debug_execution is true");
return ERROR_FAIL; return ERROR_FAIL;
@ -1688,12 +1671,22 @@ static int riscv_step(struct target *target, int current, uint32_t address,
jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE); jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
if (info->need_strict_step) { if (!current) {
if (info->xlen > 32) {
LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
info->xlen);
}
int result = register_write(target, REG_PC, address);
if (result != ERROR_OK)
return result;
}
if (info->need_strict_step || handle_breakpoints) {
int result = strict_step(target, true); int result = strict_step(target, true);
if (result != ERROR_OK) if (result != ERROR_OK)
return result; return result;
} else { } else {
return resume(target, current, address, handle_breakpoints, 0, true); return resume(target, 0, true);
} }
return ERROR_OK; return ERROR_OK;
@ -2109,14 +2102,23 @@ static int riscv_resume(struct target *target, int current, uint32_t address,
jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE); jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
if (info->need_strict_step) { if (!current) {
if (info->xlen > 32) {
LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
info->xlen);
}
int result = register_write(target, REG_PC, address);
if (result != ERROR_OK)
return result;
}
if (info->need_strict_step || handle_breakpoints) {
int result = strict_step(target, false); int result = strict_step(target, false);
if (result != ERROR_OK) if (result != ERROR_OK)
return result; return result;
} }
return resume(target, current, address, handle_breakpoints, return resume(target, debug_execution, false);
debug_execution, false);
} }
static int riscv_assert_reset(struct target *target) static int riscv_assert_reset(struct target *target)