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target/xtensa: extra debug info for "xtensa exe" failures 

- Read and display EXCCAUSE on exe error
- Clean up error messages
- Clarify "xtensa exe" documentation

Signed-off-by: ianst <ianst@cadence.com>
Change-Id: I90ed39f6afb6543c0c873301501435384b4dccbe
Reviewed-on: https://review.openocd.org/c/openocd/+/7982
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
ianst 2023-12-06 14:34:09 -08:00 committed by Evgeniy Naydanov
parent 881fd76898
commit 3d37a84b07
2 changed files with 17 additions and 10 deletions
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9
doc/openocd.texi
View File

@ -11826,13 +11826,14 @@ This feature is not well implemented and tested yet.
@end deffn @end deffn
@deffn {Command} {xtensa exe} <ascii-encoded hexadecimal instruction bytes> @deffn {Command} {xtensa exe} <ascii-encoded hexadecimal instruction bytes>
Execute arbitrary instruction(s) provided as an ascii string. The string represents an integer Execute one arbitrary instruction provided as an ascii string. The string represents an integer
number of instruction bytes, thus its length must be even. number of instruction bytes, thus its length must be even. The instruction can be of any width
that is valid for the Xtensa core configuration.
@end deffn @end deffn
@deffn {Command} {xtensa dm} (address) [value] @deffn {Command} {xtensa dm} (address) [value]
Read or write Xtensa Debug Module (DM) registers. @var{address} is required for both reads Read or write Xtensa Debug Module (DM) registers. @var{address} is required for both reads
and writes and is a 4-byte-aligned value typically between 0 and 0x3ffc. @var{value} is specified and writes and is a 4-byte-aligned value typically between 0 and 0x3ffc. @var{value} is specified
only for write accesses. only for write accesses.
@end deffn @end deffn

18
src/target/xtensa/xtensa.c
View File

@ -3483,15 +3483,21 @@ static COMMAND_HELPER(xtensa_cmd_exe_do, struct target *target)
LOG_TARGET_DEBUG(target, "execute stub: %s", CMD_ARGV[0]); LOG_TARGET_DEBUG(target, "execute stub: %s", CMD_ARGV[0]);
xtensa_queue_exec_ins_wide(xtensa, ops, oplen); /* Handles endian-swap */ xtensa_queue_exec_ins_wide(xtensa, ops, oplen); /* Handles endian-swap */
status = xtensa_dm_queue_execute(&xtensa->dbg_mod); status = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (status != ERROR_OK) if (status != ERROR_OK) {
LOG_TARGET_ERROR(target, "TIE queue execute: %d\n", status); LOG_TARGET_ERROR(target, "exec: queue error %d", status);
status = xtensa_core_status_check(target); } else {
if (status != ERROR_OK) status = xtensa_core_status_check(target);
LOG_TARGET_ERROR(target, "TIE instr execute: %d\n", status); if (status != ERROR_OK)
LOG_TARGET_ERROR(target, "exec: status error %d", status);
}
/* Reread register cache and restore saved regs after instruction execution */ /* Reread register cache and restore saved regs after instruction execution */
if (xtensa_fetch_all_regs(target) != ERROR_OK) if (xtensa_fetch_all_regs(target) != ERROR_OK)
LOG_TARGET_ERROR(target, "%s: Failed to fetch register cache (post-exec).", target_name(target)); LOG_TARGET_ERROR(target, "post-exec: register fetch error");
if (status != ERROR_OK) {
LOG_TARGET_ERROR(target, "post-exec: EXCCAUSE 0x%02" PRIx32,
xtensa_reg_get(target, XT_REG_IDX_EXCCAUSE));
}
xtensa_reg_set(target, XT_REG_IDX_EXCCAUSE, exccause); xtensa_reg_set(target, XT_REG_IDX_EXCCAUSE, exccause);
xtensa_reg_set(target, XT_REG_IDX_CPENABLE, cpenable); xtensa_reg_set(target, XT_REG_IDX_CPENABLE, cpenable);
return status; return status;