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tcl/target/ti_k3: Add a gdb-attach event hook for r5 and simplify startup function 

Since we can detect the type of target as well, make the attach
function name generic for the follow on cleanup patch on armv8 to use
as well.

Lets introduce gdb-attach event in a much cleaner fashion. We can
introduce a simpler r5_up function since we now have more descriptive
core names making the individual descriptive procs redundant.

NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior

Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I31506bb2b86e63638082640eb72aa7c4c9575e93
Reviewed-on: https://review.openocd.org/c/openocd/+/6617
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Nishanth Menon 2021-10-04 09:20:34 -05:00 committed by Antonio Borneo
parent 4b12c9e8c5
commit 3ba2b515b5
1 changed files with 16 additions and 34 deletions
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50
tcl/target/ti_k3.cfg
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@ -64,9 +64,6 @@ switch $_soc {
# AM654 has 1 cluster of 2 R5s cores. # AM654 has 1 cluster of 2 R5s cores.
set _r5_cores 2 set _r5_cores 2
set _mcu_r5_cores 2
set _main0_r5_cores 0
set _main1_r5_cores 0
set R5_NAMES {mcu_r5.0 mcu_r5.1} set R5_NAMES {mcu_r5.0 mcu_r5.1}
# Sysctrl power-ap unlock offsets # Sysctrl power-ap unlock offsets
@ -84,9 +81,6 @@ switch $_soc {
# AM642 has 2 cluster of 2 R5s cores. # AM642 has 2 cluster of 2 R5s cores.
set _r5_cores 4 set _r5_cores 4
set _mcu_r5_cores 0
set _main0_r5_cores 2
set _main1_r5_cores 2
set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1} set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000} set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000} set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
@ -103,9 +97,6 @@ switch $_soc {
# J721E has 3 clusters of 2 R5 cores each. # J721E has 3 clusters of 2 R5 cores each.
set _r5_cores 6 set _r5_cores 6
set _mcu_r5_cores 2
set _main0_r5_cores 2
set _main1_r5_cores 2
} }
j7200 { j7200 {
set _CHIPNAME j7200 set _CHIPNAME j7200
@ -117,9 +108,6 @@ switch $_soc {
# J7200 has 2 clusters of 2 R5 cores each. # J7200 has 2 clusters of 2 R5 cores each.
set _r5_cores 4 set _r5_cores 4
set _mcu_r5_cores 2
set _main0_r5_cores 2
set _main1_r5_cores 0
set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000} set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000} set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
@ -158,6 +146,14 @@ $_TARGETNAME.sysctrl configure -event gdb-attach {
halt 1000 halt 1000
} }
proc _cpu_no_smp_up {} {
set _current_target [target current]
set _current_type [$_current_target cget -type]
$_current_target arp_examine
$_current_target $_current_type dbginit
}
set _v8_smp_targets "" set _v8_smp_targets ""
for { set _core 0 } { $_core < $_armv8_cores } { incr _core } { for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
@ -206,32 +202,18 @@ for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
# inactive core examination will fail - wait till startup of additional core # inactive core examination will fail - wait till startup of additional core
target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \ target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
}
if { $_mcu_r5_cores != 0 } { $_TARGETNAME.$_r5_name configure -event gdb-attach {
proc mcu_r5_up { args } { _cpu_no_smp_up
foreach { _core } [set args] { # gdb-attach default rule
$::_TARGETNAME.mcu_r5.$_core arp_examine halt 1000
$::_TARGETNAME.mcu_r5.$_core cortex_r4 dbginit
}
} }
} }
if { $_main0_r5_cores != 0 } { proc r5_up { args } {
proc main0_r5_up { args } { foreach _core $args {
foreach { _core } [set args] { targets $_core
$::_TARGETNAME.main0_r5.$_core arp_examine _cpu_no_smp_up
$::_TARGETNAME.main0_r5.$_core cortex_r4 dbginit
}
}
}
if { $_main1_r5_cores != 0 } {
proc main1_r5_up { args } {
foreach { _core } [set args] {
$::_TARGETNAME.main1_r5.$_core arp_examine
$::_TARGETNAME.main1_r5.$_core cortex_r4 dbginit
}
} }
} }