Extended execute_fence to handle all harts
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@ -1771,13 +1771,38 @@ static void write_to_buf(uint8_t *buffer, uint64_t value, unsigned size)
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static int execute_fence(struct target *target)
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{
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int old_hartid = riscv_current_hartid(target);
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/* FIXME: For non-coherent systems we need to flush the caches right
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* here, but there's no ISA-defined way of doing that. */
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{
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struct riscv_program program;
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riscv_program_init(&program, target);
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riscv_program_fence_i(&program);
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riscv_program_fence(&program);
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int result = riscv_program_exec(&program, target);
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if (result != ERROR_OK)
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LOG_ERROR("Unable to execute fence");
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return result;
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LOG_DEBUG("Unable to execute pre-fence");
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}
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for (int i = 0; i < riscv_count_harts(target); ++i) {
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if (!riscv_hart_enabled(target, i))
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continue;
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riscv_set_current_hartid(target, i);
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struct riscv_program program;
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riscv_program_init(&program, target);
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riscv_program_fence_i(&program);
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riscv_program_fence(&program);
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int result = riscv_program_exec(&program, target);
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if (result != ERROR_OK)
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LOG_DEBUG("Unable to execute fence on hart %d", i);
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}
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riscv_set_current_hartid(target, old_hartid);
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return ERROR_OK;
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}
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static void log_memory_access(target_addr_t address, uint64_t value,
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@ -3305,19 +3330,7 @@ int riscv013_dmi_write_u64_bits(struct target *target)
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static int maybe_execute_fence_i(struct target *target)
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{
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RISCV013_INFO(info);
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RISCV_INFO(r);
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if (info->progbufsize + r->impebreak >= 2) {
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struct riscv_program program;
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riscv_program_init(&program, target);
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if (riscv_program_fence_i(&program) != ERROR_OK)
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return ERROR_FAIL;
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if (riscv_program_exec(&program, target) != ERROR_OK) {
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LOG_ERROR("Failed to execute fence.i");
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return ERROR_FAIL;
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}
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}
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return ERROR_OK;
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return execute_fence(target);
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}
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/* Helper Functions. */
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