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armv7a: remove special l2x flush-all and cache-info handlers 

This patch is on the path to unified handlers for both inner and
outer caches. It removes the special overrides installed when
an outer cache is configured.

Change-Id: I747f2762c6c8c76c700341cbf6cf500ff2a51476
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3022
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Matthias Welwarsky 2015-10-15 18:36:14 +02:00 committed by Paul Fertser
parent 4ba83e1c9b
commit 3a292a1f34
4 changed files with 11 additions and 66 deletions
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71
src/target/armv7a.c
View File

@ -401,61 +401,6 @@ static int armv7a_handle_inner_cache_info_command(struct command_context *cmd_ct
return ERROR_OK;
}
/* L2 is not specific to armv7a a specific file is needed */
static int armv7a_l2x_flush_all_data(struct target *target)
{
#define L2X0_CLEAN_INV_WAY 0x7FC
int retval = ERROR_FAIL;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
(armv7a->armv7a_mmu.armv7a_cache.outer_cache);
uint32_t base = l2x_cache->base;
uint32_t l2_way = l2x_cache->way;
uint32_t l2_way_val = (1 << l2_way) - 1;
retval = armv7a_cache_auto_flush_all_data(target);
if (retval != ERROR_OK)
return retval;
retval = target->type->write_phys_memory(target,
(uint32_t)(base+(uint32_t)L2X0_CLEAN_INV_WAY),
(uint32_t)4,
(uint32_t)1,
(uint8_t *)&l2_way_val);
return retval;
}
static int armv7a_handle_l2x_cache_info_command(struct command_context *cmd_ctx,
struct armv7a_cache_common *armv7a_cache)
{
struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
(armv7a_cache->outer_cache);
if (armv7a_cache->ctype == -1) {
command_print(cmd_ctx, "cache not yet identified");
return ERROR_OK;
}
command_print(cmd_ctx,
"L1 D-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
armv7a_cache->d_u_size.linelen,
armv7a_cache->d_u_size.associativity,
armv7a_cache->d_u_size.nsets,
armv7a_cache->d_u_size.cachesize);
command_print(cmd_ctx,
"L1 I-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
armv7a_cache->i_size.linelen,
armv7a_cache->i_size.associativity,
armv7a_cache->i_size.nsets,
armv7a_cache->i_size.cachesize);
command_print(cmd_ctx, "L2 unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
l2x_cache->base, l2x_cache->way);
return ERROR_OK;
}
/* FIXME: remove it */
static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t way)
{
@ -472,11 +417,6 @@ static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t
if (armv7a->armv7a_mmu.armv7a_cache.outer_cache)
LOG_INFO("outer cache already initialized\n");
armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
/* initialize l1 / l2x cache function */
armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache
= armv7a_l2x_flush_all_data;
armv7a->armv7a_mmu.armv7a_cache.display_cache_info =
armv7a_handle_l2x_cache_info_command;
/* initialize all target in this cluster (smp target)
* l2 cache must be configured after smp declaration */
while (head != (struct target_list *)NULL) {
@ -486,10 +426,6 @@ static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t
if (armv7a->armv7a_mmu.armv7a_cache.outer_cache)
LOG_ERROR("smp target : outer cache already initialized\n");
armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache =
armv7a_l2x_flush_all_data;
armv7a->armv7a_mmu.armv7a_cache.display_cache_info =
armv7a_handle_l2x_cache_info_command;
}
head = head->next;
}
@ -518,6 +454,9 @@ COMMAND_HANDLER(handle_cache_l2x)
int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
struct armv7a_cache_common *armv7a_cache)
{
struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
(armv7a_cache->outer_cache);
if (armv7a_cache->ctype == -1) {
command_print(cmd_ctx, "cache not yet identified");
return ERROR_OK;
@ -525,6 +464,10 @@ int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
if (armv7a_cache->display_cache_info)
armv7a_cache->display_cache_info(cmd_ctx, armv7a_cache);
if (l2x_cache != NULL)
command_print(cmd_ctx, "Outer unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
l2x_cache->base, l2x_cache->way);
return ERROR_OK;
}

3
src/target/armv7a_cache.c
View File

@ -127,7 +127,8 @@ int armv7a_cache_auto_flush_all_data(struct target *target)
} else
retval = armv7a_l1_d_cache_clean_inval_all(target);
/* FIXME: do l2x flushing here */
/* do outer cache flushing after inner caches have been flushed */
retval = arm7a_l2x_flush_all_data(target);
return retval;
}

2
src/target/armv7a_cache_l2x.c
View File

@ -46,7 +46,7 @@ static int arm7a_l2x_sanity_check(struct target *target)
/*
* clean and invalidate complete l2x cache
*/
static int arm7a_l2x_flush_all_data(struct target *target)
int arm7a_l2x_flush_all_data(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)

1
src/target/armv7a_cache_l2x.h
View File

@ -150,5 +150,6 @@ extern const struct command_registration arm7a_l2x_cache_command_handler[];
int armv7a_l2x_cache_flush_virt(struct target *target, uint32_t virt,
uint32_t size);
int arm7a_l2x_flush_all_data(struct target *target);
#endif