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aarch64: Use 64-bit reads/writes to access SCTLR_EL1 

We were previously inadvertently clearing the top 32 bits of SCTLR_EL1
during read_memory/write_memory as a result of using 32-bit operations
to access the register and because the fields used to temporarily
store the register were 32-bit. Fix it.

Change-Id: I657d7f949e1f7ab6bf90609e3f91cae09cade31a
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7939
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Peter Collingbourne 2023-10-17 19:04:00 -07:00 committed by Antonio Borneo
parent ee96a95d44
commit 393da819b1
2 changed files with 6 additions and 6 deletions
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8
src/target/aarch64.c
View File

@ -105,7 +105,7 @@ static int aarch64_restore_system_control_reg(struct target *target)
if (target_mode != ARM_MODE_ANY) if (target_mode != ARM_MODE_ANY)
armv8_dpm_modeswitch(&armv8->dpm, target_mode); armv8_dpm_modeswitch(&armv8->dpm, target_mode);
retval = armv8->dpm.instr_write_data_r0(&armv8->dpm, instr, aarch64->system_control_reg); retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr, aarch64->system_control_reg);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
@ -182,7 +182,7 @@ static int aarch64_mmu_modify(struct target *target, int enable)
if (target_mode != ARM_MODE_ANY) if (target_mode != ARM_MODE_ANY)
armv8_dpm_modeswitch(&armv8->dpm, target_mode); armv8_dpm_modeswitch(&armv8->dpm, target_mode);
retval = armv8->dpm.instr_write_data_r0(&armv8->dpm, instr, retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr,
aarch64->system_control_reg_curr); aarch64->system_control_reg_curr);
if (target_mode != ARM_MODE_ANY) if (target_mode != ARM_MODE_ANY)
@ -1055,14 +1055,14 @@ static int aarch64_post_debug_entry(struct target *target)
if (target_mode != ARM_MODE_ANY) if (target_mode != ARM_MODE_ANY)
armv8_dpm_modeswitch(&armv8->dpm, target_mode); armv8_dpm_modeswitch(&armv8->dpm, target_mode);
retval = armv8->dpm.instr_read_data_r0(&armv8->dpm, instr, &aarch64->system_control_reg); retval = armv8->dpm.instr_read_data_r0_64(&armv8->dpm, instr, &aarch64->system_control_reg);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
if (target_mode != ARM_MODE_ANY) if (target_mode != ARM_MODE_ANY)
armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY); armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg); LOG_DEBUG("System_register: %8.8" PRIx64, aarch64->system_control_reg);
aarch64->system_control_reg_curr = aarch64->system_control_reg; aarch64->system_control_reg_curr = aarch64->system_control_reg;
if (armv8->armv8_mmu.armv8_cache.info == -1) { if (armv8->armv8_mmu.armv8_cache.info == -1) {

4
src/target/aarch64.h
View File

@ -43,8 +43,8 @@ struct aarch64_common {
struct armv8_common armv8_common; struct armv8_common armv8_common;
/* Context information */ /* Context information */
uint32_t system_control_reg; uint64_t system_control_reg;
uint32_t system_control_reg_curr; uint64_t system_control_reg_curr;
/* Breakpoint register pairs */ /* Breakpoint register pairs */
int brp_num_context; int brp_num_context;