aarch64: use symbolic opcodes instead of hex values
Use opcode definitions from armv8_opcodes.h where appropriate Change-Id: Iead33fb8e62eb2dd2419ef8932f7d46c087f51a8 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
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044e4b8108
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391109505f
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@ -529,7 +529,7 @@ static int aarch64_instr_write_data_r0(struct arm_dpm *dpm,
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retval = aarch64_exec_opcode(
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a8->armv8_common.arm.target,
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0xd5330500,
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ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 0),
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&dscr);
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if (retval != ERROR_OK)
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return retval;
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@ -556,7 +556,7 @@ static int aarch64_instr_write_data_r0_64(struct arm_dpm *dpm,
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retval = aarch64_exec_opcode(
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a8->armv8_common.arm.target,
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0xd5330400,
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ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0),
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&dscr);
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if (retval != ERROR_OK)
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return retval;
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@ -577,7 +577,7 @@ static int aarch64_instr_cpsr_sync(struct arm_dpm *dpm)
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/* "Prefetch flush" after modifying execution status in CPSR */
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return aarch64_exec_opcode(target,
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ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
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DSB_SY,
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&dscr);
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}
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@ -635,7 +635,7 @@ static int aarch64_instr_read_data_r0(struct arm_dpm *dpm,
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/* write R0 to DCC */
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retval = aarch64_exec_opcode(
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a8->armv8_common.arm.target,
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0xd5130400, /* msr dbgdtr_el0, x0 */
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ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 0), /* msr dbgdtr_el0, x0 */
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&dscr);
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if (retval != ERROR_OK)
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return retval;
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@ -661,7 +661,7 @@ static int aarch64_instr_read_data_r0_64(struct arm_dpm *dpm,
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/* write R0 to DCC */
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retval = aarch64_exec_opcode(
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a8->armv8_common.arm.target,
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0xd5130400, /* msr dbgdtr_el0, x0 */
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ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0), /* msr dbgdtr_el0, x0 */
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&dscr);
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if (retval != ERROR_OK)
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return retval;
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@ -1384,8 +1384,7 @@ static int aarch64_set_breakpoint(struct target *target,
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} else if (breakpoint->type == BKPT_SOFT) {
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uint8_t code[4];
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buf_set_u32(code, 0, 32, 0xD4400000);
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buf_set_u32(code, 0, 32, ARMV8_BKPT(0x11));
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retval = target_read_memory(target,
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breakpoint->address & 0xFFFFFFFFFFFFFFFE,
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breakpoint->length, 1,
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