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added embedded ice programming while srst is asserted todo item 

git-svn-id: svn://svn.berlios.de/openocd/trunk@2710 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe 2009-09-15 09:41:09 +00:00
parent 45674af63a
commit 379386743a
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@ -114,6 +114,10 @@ Once the above are completed:
https://lists.berlios.de/pipermail/openocd-development/2009-July/009426.html
- regression: "reset halt" between 729(works) and 788(fails): @par
https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
- ARM7/9:
- add reset option to allow programming embedded ice while srst is asserted.
Some CPUs will gate the JTAG clock when srst is asserted and in this case,
it is necessary to program embedded ice and then assert srst afterwards.
- ARM923EJS:
- reset run/halt/step is not robust; needs testing to map out problems.
- ARM11 improvements (MB?)