flash/nor: add support for NXP QN908x
This patch adds support for the NXP QN908x family of Bluetooth microcontrollers, such as the QN9080. This chip features a Cortex-M4F with 512 KiB of flash on all the available versions, although the documentation suggests that there might be 256 kB versions as well. The initial support allows to read, erase and write the whole user flash area. Three new sub-commands under the new "qn908x" command are added in this patch as well: disable_wdog to disabled the watchdog, mass_erase to perform a mass erase and allow_brick to allow programming images that disable the SWD interface. Disabling the watchdog is required after a "reset halt" in order to run the CRC algorithm from RAM when verifying the chip. However, this is not done automatically on probing or other initialization since disabling the watchdog might interfere with debugging real applications. The "mass_erase" command allows to erase the whole flash without probing it, since in some scenarios the chip can be locked such that no flash or ram can be accessed from the SWD interface, allowing only to run a mass_erase to be able to flash the program. The flashing process allows to compute a checksum, similar to the lpc2000 driver "calc_checksum" but done over a different region of the memory. This checksum is required to be present for the QN908x bootloader ROM to boot, and otherwise is useless. As with the lpc2000 design, verification when using "calc_checksum" is expected to fail if the checksum was not valid in the image being verified. This was manually tested on a QN9080, including the scan-view, AddressSanitizer/UBSan and test coverage configurations. Change-Id: Ibd6d8f3608654294795085fcaaffb448b77cc58b Co-developed-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de> Signed-off-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de> Signed-off-by: iosabi <iosabi@protonmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/5584 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
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iosabi
Antonio Borneo
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doc/openocd.texi
110
doc/openocd.texi
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@ -7341,6 +7341,116 @@ Note: only Main and Work flash regions support Erase operation.
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@end deffn
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@end deffn
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@deffn {Flash Driver} {qn908x}
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The NXP QN908x microcontrollers feature a Cortex-M4F with integrated Bluetooth
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LE 5 support and an internal flash of up to 512 KiB. These chips only support
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the SWD interface.
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The @var{qn908x} driver uses the internal "Flash Memory Controller" block via
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SWD to erase, program and read the internal flash. This driver does not
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support the ISP (In-System Programming) mode which is an alternate way to
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program the flash via UART, SPI or USB.
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The internal flash is 512 KiB in size in all released chips and it starts at
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the address 0x01000000, although it can be mapped to address 0 and it is
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aliased to other addresses. This driver only recognizes the bank starting at
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address 0x01000000.
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The internal bootloader stored in ROM is in charge of loading and verifying
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the image from flash, or enter ISP mode. The programmed image must start at
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the beginning of the flash and contain a valid header and a matching CRC32
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checksum. Additionally, the image header contains a "Code Read Protection"
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(CRP) word which indicates whether SWD access is enabled, as well as whether
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ISP mode is enabled. Therefore, it is possible to program an image that
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disables SWD and ISP making it impossible to program another image in the
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future through these interfaces, or even debug the current image. While this is
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a valid use case for production deployments where the chips are locked down, by
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default this driver doesn't allow such images that disable the SWD interface.
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To program such images see the @command{qn908x allow_brick} command.
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Apart from the CRP field which is located in the image header, the last page
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of the flash memory contains a "Flash lock and protect" descriptor which allows
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to individually protect each 2 KiB page, as well as disabling SWD access to the
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flash and RAM. If this access is disabled it is not possible to read, erase or
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program individual pages from the SWD interface or even access the read-only
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"Flash information page" with information about the bootloader version and
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flash size. However when this protection is in place, it is still possible to
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mass erase the whole chip and then program a new image, for which you can use
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the @command{qn908x mass_erase}.
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Example:
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@example
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flash bank $FLASHNAME qn908x 0x01000000 0 0 0 $TARGETNAME calc_checksum
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@end example
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Parameters:
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@itemize
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@item @option{calc_checksum} optional parameter to compute the required
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checksum of the first bytes in the vector table.
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@quotation Note
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If the checksum in the header of your image is invalid and you don't provide the
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@option{calc_checksum} option the boot ROM will not boot your image and it may
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render the flash inaccessible. On the other hand, if you use this option to
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compute the checksum keep in mind that @command{verify_image} will fail on
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those four bytes of the checksum since those bytes in the flash will have the
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updated checksum.
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@end quotation
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@end itemize
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@deffn {Command} {qn908x allow_brick}
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Allow the qn908x driver to program images with a "Code Read Protection" byte
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that disables the SWD access. Programming such image will cause OpenOCD to
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not be able to reach the target over SWD anymore after the new image is
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programmed and its configuration takes effect, e.g. after a reboot. After
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executing @command{qn908x allow_brick} these images will be allowed to be
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programmed when writing to the flash.
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@end deffn
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@deffn {Command} {qn908x disable_wdog}
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Disable the watchdog timer (WDT) by resetting its CTRL field. The WDT starts
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enabled after a @command{reset halt} and it doesn't run while the target is
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halted. However, the verification process in this driver uses the generic
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Cortex-M verification process which executes a payload in RAM and thus
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requires the watchdog to be disabled before running @command{verify_image}
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after a reset halt or any other condition where the watchdog is running.
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Note that this is not done automatically and you must run this command in
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those scenarios.
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@end deffn
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@deffn {Command} {qn908x mass_erase}
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Erases the complete flash using the mass_erase method. Mass erase is only
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allowed if enabled in the Lock Status Register 8 (LOCK_STAT_8) which is read
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from the last sector of the flash on boot. However, this mass_erase lock
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protection can be bypassed and this command does so automatically.
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In the same LOCK_STAT_8 the flash and RAM access from SWD can be disabled by
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setting two bits in this register. After a mass_erase, all the bits of the
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flash would be set, making it the default to restrict SWD access to the flash
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and RAM regions. This new after erase LOCK_STAT_8 value only takes effect after
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being read from flash on the next reboot for example. After a mass_erase the
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LOCK_STAT_8 register is changed by the hardware to allow access to flash and
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RAM regardless of the value on flash, but only right after a mass_erase and
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until the next boot. Therefore it is possible to perform a mass_erase, program
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a new image, verify it and then reboot to a valid image that's locked from the
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SWD access.
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The @command{qn908x mass_erase} command clears the bits that would be loaded
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from the flash into LOCK_STAT_8 after erasing the whole chip to allow SWD
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access for debugging or re-flashing an image without a mass_erase by default.
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If the image being programmed also programs the last page of the flash with its
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own settings, this mass_erase behavior will interfere with that write since a
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new erase of at least the last page would need to be performed before writing
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to it again. For this reason the optional @option{keep_lock} argument can be
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used to leave the flash and RAM lock set. For development environments, the
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default behavior is desired.
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The mass erase locking mechanism is independent from the individual page
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locking bits, so it is possible that you can't erase a given page that is
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locked and you can't unprotect that page because the locking bits are also
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locked, but can still mass erase the whole flash.
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@end deffn
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@end deffn
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@deffn {Flash Driver} {rp2040}
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Supports RP2040 "Raspberry Pi Pico" microcontroller.
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RP2040 is a dual-core device with two CM0+ cores. Both cores share the same
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@ -54,6 +54,7 @@ NOR_DRIVERS = \
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%D%/psoc4.c \
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%D%/psoc5lp.c \
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%D%/psoc6.c \
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%D%/qn908x.c \
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%D%/renesas_rpchf.c \
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%D%/rp2040.c \
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%D%/rsl10.c \
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@ -284,6 +284,7 @@ extern const struct flash_driver psoc5lp_eeprom_flash;
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extern const struct flash_driver psoc5lp_flash;
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extern const struct flash_driver psoc5lp_nvl_flash;
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extern const struct flash_driver psoc6_flash;
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extern const struct flash_driver qn908x_flash;
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extern const struct flash_driver renesas_rpchf_flash;
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extern const struct flash_driver rp2040_flash;
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extern const struct flash_driver rsl10_flash;
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@ -61,6 +61,7 @@ static const struct flash_driver * const flash_drivers[] = {
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&psoc5lp_eeprom_flash,
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&psoc5lp_nvl_flash,
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&psoc6_flash,
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&qn908x_flash,
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&renesas_rpchf_flash,
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&rp2040_flash,
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&sh_qspi_flash,
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,38 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# NXP QN908x Cortex-M4F with 128 KiB SRAM
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source [find target/swj-dp.tcl]
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set CHIPNAME qn908x
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set CHIPSERIES qn9080
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if { ![info exists WORKAREASIZE] } {
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set WORKAREASIZE 0x20000
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}
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# SWD IDCODE (Cortex M4).
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set CPUTAPID 0x2ba01477
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swj_newdap $CHIPNAME cpu -irlen 4 -expected-id $CPUTAPID
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dap create $CHIPNAME.dap -chain-position $CHIPNAME.cpu
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set TARGETNAME $CHIPNAME.cpu
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target create $TARGETNAME cortex_m -dap $CHIPNAME.dap
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# SRAM is mapped at 0x04000000.
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$TARGETNAME configure -work-area-phys 0x04000000 -work-area-size $WORKAREASIZE
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# flash bank <name> qn908x <base> <size> 0 0 <target#> [calc_checksum]
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# The base must be set as 0x01000000, and the size parameter is unused.
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set FLASHNAME $CHIPNAME.flash
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flash bank $FLASHNAME qn908x 0x01000000 0 0 0 $TARGETNAME calc_checksum
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# We write directly to flash memory over this adapter interface. For debugging
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# this could in theory be faster (the Core clock on reset is normally at 32MHz),
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# but for flashing 1MHz is more reliable.
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adapter speed 1000
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# Delay on reset line.
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adapter srst delay 200
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cortex_m reset_config sysresetreq
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