- added patch to solve problem with AT91SAM7SE MCU have 3, rather than just 2 GPNVM bits.
(Thanks to Pavel for the patch) git-svn-id: svn://svn.berlios.de/openocd/trunk@317 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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@ -467,8 +467,8 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
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if (at91sam7_info->cidr_arch == 0x72 )
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{
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at91sam7_info->num_nvmbits = 2;
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at91sam7_info->nvmbits = (status>>8)&0x03;
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at91sam7_info->num_nvmbits = 3;
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at91sam7_info->nvmbits = (status>>8)&0x07;
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bank->base = 0x100000;
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bank->bus_width = 4;
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if (bank->size==0x80000) /* AT91SAM7SE512 */
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@ -892,7 +892,7 @@ int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)
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}
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/*
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* On AT91SAM7S: When the gpnmv bits are set with
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* On AT91SAM7S: When the gpnvm bits are set with
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* > at91sam7 gpnvm 0 bitnr set
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* the changes are not visible in the flash controller status register MC_FSR
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* until the processor has been reset.
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