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target/cortex_m: minor refactoring in cortex_m_store_core_reg_u32() 

Unlike cortex_m_load_core_reg_u32() storing core register uses
the same code pattern around DHCSR read as offered by the convenience
helper cortex_m_read_dhcsr_atomic_sticky().

Use the helper.

Change-Id: Ia947204944a8b549f3c2be7fb2f717aad18970c4
SeeAlso: 65d7629183 (cortex_m: poll S_REGRDY on register r/w)
SeeAlso: 0dcf95c717 (target/cortex_m: cumulate DHCSR sticky bits)
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6767
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Tomas Vanek 2021-12-08 22:11:32 +01:00 committed by Antonio Borneo
parent 1e07079dee
commit 33fa237b2f
1 changed files with 1 additions and 3 deletions
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4
src/target/cortex_m.c
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@ -397,11 +397,9 @@ static int cortex_m_store_core_reg_u32(struct target *target,
/* check if value is written into register */ /* check if value is written into register */
then = timeval_ms(); then = timeval_ms();
while (1) { while (1) {
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, retval = cortex_m_read_dhcsr_atomic_sticky(target);
&cortex_m->dcb_dhcsr);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
if (cortex_m->dcb_dhcsr & S_REGRDY) if (cortex_m->dcb_dhcsr & S_REGRDY)
break; break;
if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) { if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) {