riscv-compliance: whitespace fixes
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@ -1975,7 +1975,7 @@ static int riscv013_halt_current_hart(struct target *target)
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/* Issue the halt command, and then wait for the current hart to halt. */
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/* Issue the halt command, and then wait for the current hart to halt. */
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uint32_t dmcontrol = dmi_read(target, DMI_DMCONTROL);
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uint32_t dmcontrol = dmi_read(target, DMI_DMCONTROL);
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dmcontrol |= DMI_DMCONTROL_HALTREQ;
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dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HALTREQ, 1);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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for (size_t i = 0; i < 256; ++i)
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for (size_t i = 0; i < 256; ++i)
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if (riscv_is_halted(target))
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if (riscv_is_halted(target))
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@ -1991,7 +1991,7 @@ static int riscv013_halt_current_hart(struct target *target)
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return ERROR_FAIL;
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return ERROR_FAIL;
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}
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}
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dmcontrol &= ~DMI_DMCONTROL_HALTREQ;
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dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HALTREQ, 0);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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return ERROR_OK;
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return ERROR_OK;
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@ -2255,8 +2255,6 @@ int riscv013_test_compliance(struct target *target) {
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COMPLIANCE_TEST(((testvar == 0) || (get_field(dmcontrol, DMI_DMCONTROL_HASEL)) == 0), "DMCONTROL.hasel can be 0 or RW.");
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COMPLIANCE_TEST(((testvar == 0) || (get_field(dmcontrol, DMI_DMCONTROL_HASEL)) == 0), "DMCONTROL.hasel can be 0 or RW.");
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//TODO: test that hamask registers exist if hasel does.
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//TODO: test that hamask registers exist if hasel does.
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// TODO: ndmreset
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// haltreq
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// haltreq
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riscv_halt_all_harts(target);
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riscv_halt_all_harts(target);
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// Writing haltreq should not cause any problems for a halted hart, but we
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// Writing haltreq should not cause any problems for a halted hart, but we
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