From 30b0e9af8d1e68ee051ac62dd0e27c920fb396bd Mon Sep 17 00:00:00 2001
From: Phil Kirkpatrick <p.kirkpatrick@reflexaerospace.com>
Date: Tue, 9 May 2023 11:04:24 +0200
Subject: [PATCH] tcl/target: Add support for TMS570LC43xx

Added support for TMS570LC43xx series parts.  This uses the pre-existing
ti_tms570.cfg parent config.  In ti_tms570.cfg, dbgbase was changed.
Note 1: Based on the following TI E2E post, the previous dbgbase was wrong
and the new value isn't due to a difference in parts.
Link: https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1106954/tms570ls3137-debugging-with-openocd
Note 2: Both the previous dbgbase and the one suggested in the TI E2E post
have the 2 LSB set. In the current version of OpenOCD, this will cause
cortex_a_read_cpu_memory_fast and cortex_a_write_cpu_memory_fast to fail
due to an alignment checks in
mem_ap_<read/write>_buf_noincr()->mem_ap_<read/write>().
In all other uses of dbgbase for arm cortex parts, the 2 LSB are masked
and ignored.

Change-Id: Ic936722e5a4cfc7161b0df1fe3325ee12fd901c6
Signed-off-by: Phil Kirkpatrick <p.kirkpatrick@reflexaerospace.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7682
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
---
 tcl/target/ti_tms570.cfg       | 12 +++---------
 tcl/target/ti_tms570lc43xx.cfg |  6 ++++++
 2 files changed, 9 insertions(+), 9 deletions(-)
 create mode 100644 tcl/target/ti_tms570lc43xx.cfg

diff --git a/tcl/target/ti_tms570.cfg b/tcl/target/ti_tms570.cfg
index 213fb094b..18e0d8294 100644
--- a/tcl/target/ti_tms570.cfg
+++ b/tcl/target/ti_tms570.cfg
@@ -22,7 +22,7 @@ source [find target/icepick.cfg]
 if { [info exists DAP_TAPID] } {
 	set _DAP_TAPID $DAP_TAPID
 }
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable -ignore-version
 jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
 
 # ICEpick-C (JTAG route controller)
@@ -35,10 +35,7 @@ set _JRC_TAPID2 0x0B7B302F
 set _JRC_TAPID3 0x0B95502F
 set _JRC_TAPID4 0x0B97102F
 set _JRC_TAPID5 0x0D8A002F
-set _JRC_TAPID6 0x2B8A002F
-set _JRC_TAPID7 0x2D8A002F
-set _JRC_TAPID8 0x3B8A002F
-set _JRC_TAPID9 0x3D8A002F
+set _JRC_TAPID6 0x0B8A002F
 
 
 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
@@ -48,9 +45,6 @@ jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
 	-expected-id $_JRC_TAPID4 \
 	-expected-id $_JRC_TAPID5 \
 	-expected-id $_JRC_TAPID6 \
-	-expected-id $_JRC_TAPID7 \
-	-expected-id $_JRC_TAPID8 \
-	-expected-id $_JRC_TAPID9 \
 	-ignore-version
 jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
@@ -60,7 +54,7 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 # Cortex-R4 target
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \
-	-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003
+	-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80001000
 
 # TMS570 uses quirky BE-32 mode
 $_CHIPNAME.dap ti_be_32_quirks 1
diff --git a/tcl/target/ti_tms570lc43xx.cfg b/tcl/target/ti_tms570lc43xx.cfg
new file mode 100644
index 000000000..ffda989f9
--- /dev/null
+++ b/tcl/target/ti_tms570lc43xx.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set DAP_TAPID 0x0B95A02F
+set JRC_TAPID 0x0B95A02F
+
+source [find target/ti_tms570.cfg]