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OpenOCD: fix code indentation 

Fix checkpatch errors

	ERROR:SUSPECT_CODE_INDENT: suspect code indent for
	conditional statements

Change-Id: I94d4fa5720c25dd2fb0334a824cd9026babcce4e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8497
Tested-by: jenkins
This commit is contained in:
Antonio Borneo 2024-09-16 13:45:19 +02:00
parent 8e89a8af63
commit 3099547069
17 changed files with 72 additions and 83 deletions
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6
src/helper/log.c
View File

@ -272,9 +272,9 @@ void log_init(void)
if (debug_env) {
int value;
int retval = parse_int(debug_env, &value);
if (retval == ERROR_OK &&
debug_level >= LOG_LVL_SILENT &&
debug_level <= LOG_LVL_DEBUG_IO)
if (retval == ERROR_OK
&& debug_level >= LOG_LVL_SILENT
&& debug_level <= LOG_LVL_DEBUG_IO)
debug_level = value;
}

6
src/rtos/hwthread.c
View File

@ -154,9 +154,8 @@ static int hwthread_update_threads(struct rtos *rtos)
if (curr->debug_reason == DBG_REASON_SINGLESTEP) {
current_reason = curr->debug_reason;
current_thread = tid;
} else
} else if (curr->debug_reason == DBG_REASON_BREAKPOINT) {
/* multiple breakpoints, prefer gdbs' threadid */
if (curr->debug_reason == DBG_REASON_BREAKPOINT) {
if (tid == rtos->current_threadid)
current_thread = tid;
}
@ -176,8 +175,7 @@ static int hwthread_update_threads(struct rtos *rtos)
curr->debug_reason == DBG_REASON_BREAKPOINT) {
current_reason = curr->debug_reason;
current_thread = tid;
} else
if (curr->debug_reason == DBG_REASON_DBGRQ) {
} else if (curr->debug_reason == DBG_REASON_DBGRQ) {
if (tid == rtos->current_threadid)
current_thread = tid;
}

3
src/rtos/linux.c
View File

@ -624,7 +624,7 @@ static struct threads *liste_add_task(struct threads *task_list, struct threads
{
t->next = NULL;
if (!*last)
if (!*last) {
if (!task_list) {
task_list = t;
return task_list;
@ -637,6 +637,7 @@ static struct threads *liste_add_task(struct threads *task_list, struct threads
temp->next = t;
*last = t;
return task_list;
}
} else {
(*last)->next = t;
*last = t;

10
src/target/arc.c
View File

@ -719,13 +719,13 @@ static int arc_configure(struct target *target)
LOG_TARGET_DEBUG(target, "Configuring ARC ICCM and DCCM");
/* Configuring DCCM if DCCM_BUILD and AUX_DCCM are known registers. */
if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true) &&
arc_reg_get_by_name(target->reg_cache, "aux_dccm", true))
if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true)
&& arc_reg_get_by_name(target->reg_cache, "aux_dccm", true))
CHECK_RETVAL(arc_configure_dccm(target));
/* Configuring ICCM if ICCM_BUILD and AUX_ICCM are known registers. */
if (arc_reg_get_by_name(target->reg_cache, "iccm_build", true) &&
arc_reg_get_by_name(target->reg_cache, "aux_iccm", true))
if (arc_reg_get_by_name(target->reg_cache, "iccm_build", true)
&& arc_reg_get_by_name(target->reg_cache, "aux_iccm", true))
CHECK_RETVAL(arc_configure_iccm(target));
return ERROR_OK;
@ -1067,9 +1067,7 @@ static int arc_poll(struct target *target)
LOG_TARGET_DEBUG(target, "Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
"target is still running");
}
} else if (target->state == TARGET_DEBUG_RUNNING) {
target->state = TARGET_HALTED;
LOG_TARGET_DEBUG(target, "ARC core is in debug running mode");

2
src/target/armv4_5.c
View File

@ -1342,7 +1342,7 @@ int arm_get_gdb_reg_list(struct target *target,
if (arm_core_regs[i].mode == ARM_MODE_HYP
&& arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
continue;
(*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
(*reg_list)[reg_index] = &arm->core_cache->reg_list[i];
}
/* When we supply the target description, there is no need for fake FPA */

9
src/target/armv7a_mmu.c
View File

@ -260,8 +260,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
/* skip empty entries in the first level table */
if ((first_lvl_descriptor & 3) == 0) {
pt_idx++;
} else
if ((first_lvl_descriptor & 0x40002) == 2) {
} else if ((first_lvl_descriptor & 0x40002) == 2) {
/* section descriptor */
uint32_t va_range = 1024*1024-1; /* 1MB range */
uint32_t va_start = pt_idx << 20;
@ -273,8 +272,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
LOG_USER("SECT: VA[%8.8"PRIx32" -- %8.8"PRIx32"]: PA[%8.8"PRIx32" -- %8.8"PRIx32"] %s",
va_start, va_end, pa_start, pa_end, l1_desc_bits_to_string(first_lvl_descriptor, afe));
pt_idx++;
} else
if ((first_lvl_descriptor & 0x40002) == 0x40002) {
} else if ((first_lvl_descriptor & 0x40002) == 0x40002) {
/* supersection descriptor */
uint32_t va_range = 16*1024*1024-1; /* 16MB range */
uint32_t va_start = pt_idx << 20;
@ -310,8 +308,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
if ((second_lvl_descriptor & 3) == 0) {
/* skip entry */
pt2_idx++;
} else
if ((second_lvl_descriptor & 3) == 1) {
} else if ((second_lvl_descriptor & 3) == 1) {
/* large page */
uint32_t va_range = 64*1024-1; /* 64KB range */
uint32_t va_start = (pt_idx << 20) + (pt2_idx << 12);

17
src/target/cortex_a.c
View File

@ -1324,21 +1324,21 @@ static int cortex_a_set_breakpoint(struct target *target,
brp_list[brp_i].value);
} else if (breakpoint->type == BKPT_SOFT) {
uint8_t code[4];
if (breakpoint->length == 2) {
/* length == 2: Thumb breakpoint */
if (breakpoint->length == 2)
buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
else
} else if (breakpoint->length == 3) {
/* length == 3: Thumb-2 breakpoint, actual encoding is
* a regular Thumb BKPT instruction but we replace a
* 32bit Thumb-2 instruction, so fix-up the breakpoint
* length
*/
if (breakpoint->length == 3) {
buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
breakpoint->length = 4;
} else
} else {
/* length == 4, normal ARM breakpoint */
buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
}
retval = target_read_memory(target,
breakpoint->address & 0xFFFFFFFE,
@ -1348,8 +1348,7 @@ static int cortex_a_set_breakpoint(struct target *target,
return retval;
/* make sure data cache is cleaned & invalidated down to PoC */
armv7a_cache_flush_virt(target, breakpoint->address,
breakpoint->length);
armv7a_cache_flush_virt(target, breakpoint->address, breakpoint->length);
retval = target_write_memory(target,
breakpoint->address & 0xFFFFFFFE,
@ -1358,10 +1357,8 @@ static int cortex_a_set_breakpoint(struct target *target,
return retval;
/* update i-cache at breakpoint location */
armv7a_l1_d_cache_inval_virt(target, breakpoint->address,
breakpoint->length);
armv7a_l1_i_cache_inval_virt(target, breakpoint->address,
breakpoint->length);
armv7a_l1_d_cache_inval_virt(target, breakpoint->address, breakpoint->length);
armv7a_l1_i_cache_inval_virt(target, breakpoint->address, breakpoint->length);
breakpoint->is_set = true;
}

6
src/target/stm8.c
View File

@ -689,15 +689,13 @@ static int stm8_write_flash(struct target *target, enum mem_type type,
if (stm8->flash_ncr2)
stm8_write_u8(target, stm8->flash_ncr2, ~(PRG + opt));
blocksize = blocksize_param;
} else
if ((bytecnt >= 4) && ((address & 0x3) == 0)) {
} else if ((bytecnt >= 4) && ((address & 0x3) == 0)) {
if (stm8->flash_cr2)
stm8_write_u8(target, stm8->flash_cr2, WPRG + opt);
if (stm8->flash_ncr2)
stm8_write_u8(target, stm8->flash_ncr2, ~(WPRG + opt));
blocksize = 4;
} else
if (blocksize != 1) {
} else if (blocksize != 1) {
if (stm8->flash_cr2)
stm8_write_u8(target, stm8->flash_cr2, opt);
if (stm8->flash_ncr2)