OpenOCD: fix code indentation

Fix checkpatch errors

	ERROR:SUSPECT_CODE_INDENT: suspect code indent for
	conditional statements

Change-Id: I94d4fa5720c25dd2fb0334a824cd9026babcce4e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8497
Tested-by: jenkins

src/flash/nor/fespi.c

@@ -751,9 +751,9 @@ static int fespi_probe(struct flash_bank *bank)
 				target_device->name, bank->base);
 
 	} else {
-	  LOG_DEBUG("Assuming FESPI as specified at address " TARGET_ADDR_FMT
+		LOG_DEBUG("Assuming FESPI as specified at address " TARGET_ADDR_FMT
-			  " with ctrl at " TARGET_ADDR_FMT, fespi_info->ctrl_base,
+				  " with ctrl at " TARGET_ADDR_FMT, fespi_info->ctrl_base,
-			  bank->base);
+				  bank->base);
 	}
 
 	/* read and decode flash ID; returns in SW mode */

src/flash/nor/kinetis_ke.c

@@ -1005,7 +1005,7 @@ static int kinetis_ke_write(struct flash_bank *bank, const uint8_t *buffer,
 
 	result = kinetis_ke_stop_watchdog(bank->target);
 	if (result != ERROR_OK)
-			return result;
+		return result;
 
 	result = kinetis_ke_prepare_flash(bank);
 	if (result != ERROR_OK)

src/flash/nor/niietcm4.c

@@ -311,7 +311,7 @@ static int niietcm4_uflash_page_erase(struct flash_bank *bank, int page_num, int
 	/* status check */
 	retval = niietcm4_uopstatus_check(bank);
 	if (retval != ERROR_OK)
-			return retval;
+		return retval;
 
 	return retval;
 }
@@ -394,7 +394,7 @@ COMMAND_HANDLER(niietcm4_handle_uflash_read_byte_command)
 	uint32_t uflash_data;
 
 	if (strcmp("info", CMD_ARGV[0]) == 0)
-			uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ_IFB;
+		uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ_IFB;
 	else if (strcmp("main", CMD_ARGV[0]) == 0)
 		uflash_cmd = UFMC_MAGIC_KEY | UFMC_READ;
 	else
@@ -539,7 +539,7 @@ COMMAND_HANDLER(niietcm4_handle_uflash_erase_command)
 	int mem_type;
 
 	if (strcmp("info", CMD_ARGV[0]) == 0)
-			mem_type = 1;
+		mem_type = 1;
 	else if (strcmp("main", CMD_ARGV[0]) == 0)
 		mem_type = 0;
 	else

src/flash/nor/psoc4.c

@@ -384,15 +384,15 @@ static int psoc4_get_silicon_id(struct flash_bank *bank, uint32_t *silicon_id, u
 	 * bit 7..0   family ID (lowest 8 bits)
 	 */
 	if (silicon_id)
-			*silicon_id = ((part0 & 0x0000ffff) << 16)
+		*silicon_id = ((part0 & 0x0000ffff) << 16)
-				    | ((part0 & 0x00ff0000) >> 8)
+					  | ((part0 & 0x00ff0000) >> 8)
-				    | (part1 & 0x000000ff);
+					  | (part1 & 0x000000ff);
 
 	if (family_id)
-			*family_id = part1 & 0x0fff;
+		*family_id = part1 & 0x0fff;
 
 	if (protection)
-			*protection = (part1 >> 12) & 0x0f;
+		*protection = (part1 >> 12) & 0x0f;
 
 	return ERROR_OK;
 }

src/helper/log.c

@@ -272,10 +272,10 @@ void log_init(void)
 	if (debug_env) {
 		int value;
 		int retval = parse_int(debug_env, &value);
-		if (retval == ERROR_OK &&
+		if (retval == ERROR_OK
-				debug_level >= LOG_LVL_SILENT &&
+				&& debug_level >= LOG_LVL_SILENT
-				debug_level <= LOG_LVL_DEBUG_IO)
+				&& debug_level <= LOG_LVL_DEBUG_IO)
-				debug_level = value;
+			debug_level = value;
 	}
 
 	if (!log_output)

src/rtos/hwthread.c

@@ -154,9 +154,8 @@ static int hwthread_update_threads(struct rtos *rtos)
 				if (curr->debug_reason == DBG_REASON_SINGLESTEP) {
 					current_reason = curr->debug_reason;
 					current_thread = tid;
-				} else
+				} else if (curr->debug_reason == DBG_REASON_BREAKPOINT) {
-				/* multiple breakpoints, prefer gdbs' threadid */
+					/* multiple breakpoints, prefer gdbs' threadid */
-				if (curr->debug_reason == DBG_REASON_BREAKPOINT) {
 					if (tid == rtos->current_threadid)
 						current_thread = tid;
 				}
@@ -176,8 +175,7 @@ static int hwthread_update_threads(struct rtos *rtos)
 						curr->debug_reason == DBG_REASON_BREAKPOINT) {
 					current_reason = curr->debug_reason;
 					current_thread = tid;
-				} else
+				} else if (curr->debug_reason == DBG_REASON_DBGRQ) {
-				if (curr->debug_reason == DBG_REASON_DBGRQ) {
 					if (tid == rtos->current_threadid)
 						current_thread = tid;
 				}

src/rtos/linux.c

@@ -624,7 +624,7 @@ static struct threads *liste_add_task(struct threads *task_list, struct threads
 {
 	t->next = NULL;
 
-	if (!*last)
+	if (!*last) {
 		if (!task_list) {
 			task_list = t;
 			return task_list;
@@ -637,7 +637,8 @@ static struct threads *liste_add_task(struct threads *task_list, struct threads
 			temp->next = t;
 			*last = t;
 			return task_list;
-		} else {
+		}
+	} else {
 		(*last)->next = t;
 		*last = t;
 		return task_list;

src/target/aarch64.c

@@ -2908,9 +2908,9 @@ static int aarch64_jim_configure(struct target *target, struct jim_getopt_info *
 
 	pc = (struct aarch64_private_config *)target->private_config;
 	if (!pc) {
-			pc = calloc(1, sizeof(struct aarch64_private_config));
+		pc = calloc(1, sizeof(struct aarch64_private_config));
-			pc->adiv5_config.ap_num = DP_APSEL_INVALID;
+		pc->adiv5_config.ap_num = DP_APSEL_INVALID;
-			target->private_config = pc;
+		target->private_config = pc;
 	}
 
 	/*

src/target/arc.c

@@ -388,7 +388,7 @@ static int arc_build_reg_cache(struct target *target)
 	}
 
 	list_for_each_entry(reg_desc, &arc->aux_reg_descriptions, list) {
-		 CHECK_RETVAL(arc_init_reg(target, &reg_list[i],  reg_desc, i));
+		CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, i));
 
 		LOG_TARGET_DEBUG(target, "reg n=%3li name=%3s group=%s feature=%s", i,
 			reg_list[i].name, reg_list[i].group,
@@ -464,7 +464,7 @@ static int arc_build_bcr_reg_cache(struct target *target)
 	}
 
 	list_for_each_entry(reg_desc, &arc->bcr_reg_descriptions, list) {
-		 CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, gdb_regnum));
+		CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, gdb_regnum));
 		/* BCRs always semantically, they are just read-as-zero, if there is
 		 * not real register. */
 		reg_list[i].exist = true;
@@ -719,14 +719,14 @@ static int arc_configure(struct target *target)
 	LOG_TARGET_DEBUG(target, "Configuring ARC ICCM and DCCM");
 
 	/* Configuring DCCM if DCCM_BUILD and AUX_DCCM are known registers. */
-	if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true) &&
+	if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true)
-	    arc_reg_get_by_name(target->reg_cache, "aux_dccm", true))
+		    && arc_reg_get_by_name(target->reg_cache, "aux_dccm", true))
-				CHECK_RETVAL(arc_configure_dccm(target));
+		CHECK_RETVAL(arc_configure_dccm(target));
 
 	/* Configuring ICCM if ICCM_BUILD and AUX_ICCM are known registers. */
-	if (arc_reg_get_by_name(target->reg_cache, "iccm_build", true) &&
+	if (arc_reg_get_by_name(target->reg_cache, "iccm_build", true)
-	    arc_reg_get_by_name(target->reg_cache, "aux_iccm", true))
+			&& arc_reg_get_by_name(target->reg_cache, "aux_iccm", true))
-				CHECK_RETVAL(arc_configure_iccm(target));
+		CHECK_RETVAL(arc_configure_iccm(target));
 
 	return ERROR_OK;
 }
@@ -1067,9 +1067,7 @@ static int arc_poll(struct target *target)
 			LOG_TARGET_DEBUG(target, "Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
 						"target is still running");
 		}
-
 	} else if (target->state == TARGET_DEBUG_RUNNING) {
-
 		target->state = TARGET_HALTED;
 		LOG_TARGET_DEBUG(target, "ARC core is in debug running mode");
 

src/target/armv4_5.c

@@ -1301,11 +1301,11 @@ int arm_get_gdb_reg_list(struct target *target,
 		*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
 
 		for (i = 0; i < 16; i++)
-				(*reg_list)[i] = arm_reg_current(arm, i);
+			(*reg_list)[i] = arm_reg_current(arm, i);
 
 		/* For GDB compatibility, take FPA registers size into account and zero-fill it*/
 		for (i = 16; i < 24; i++)
-				(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
+			(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
 		(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
 
 		(*reg_list)[25] = arm->cpsr;
@@ -1330,25 +1330,25 @@ int arm_get_gdb_reg_list(struct target *target,
 		*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
 
 		for (i = 0; i < 16; i++)
-				(*reg_list)[i] = arm_reg_current(arm, i);
+			(*reg_list)[i] = arm_reg_current(arm, i);
 
 		for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
-				int reg_index = arm->core_cache->reg_list[i].number;
+			int reg_index = arm->core_cache->reg_list[i].number;
 
-				if (arm_core_regs[i].mode == ARM_MODE_MON
+			if (arm_core_regs[i].mode == ARM_MODE_MON
 					&& arm->core_type != ARM_CORE_TYPE_SEC_EXT
 					&& arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
-					continue;
+				continue;
-				if (arm_core_regs[i].mode == ARM_MODE_HYP
+			if (arm_core_regs[i].mode == ARM_MODE_HYP
 					&& arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
-					continue;
+				continue;
-				(*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
+			(*reg_list)[reg_index] = &arm->core_cache->reg_list[i];
 		}
 
 		/* When we supply the target description, there is no need for fake FPA */
 		for (i = 16; i < 24; i++) {
-				(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
+			(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
-				(*reg_list)[i]->size = 0;
+			(*reg_list)[i]->size = 0;
 		}
 		(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
 		(*reg_list)[24]->size = 0;

src/target/armv7a_mmu.c

@@ -260,8 +260,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
 		/* skip empty entries in the first level table */
 		if ((first_lvl_descriptor & 3) == 0) {
 			pt_idx++;
-		} else
+		} else if ((first_lvl_descriptor & 0x40002) == 2) {
-		if ((first_lvl_descriptor & 0x40002) == 2) {
 			/* section descriptor */
 			uint32_t va_range = 1024*1024-1; /* 1MB range */
 			uint32_t va_start = pt_idx << 20;
@@ -273,8 +272,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
 			LOG_USER("SECT: VA[%8.8"PRIx32" -- %8.8"PRIx32"]: PA[%8.8"PRIx32" -- %8.8"PRIx32"] %s",
 				va_start, va_end, pa_start, pa_end, l1_desc_bits_to_string(first_lvl_descriptor, afe));
 			pt_idx++;
-		} else
+		} else if ((first_lvl_descriptor & 0x40002) == 0x40002) {
-		if ((first_lvl_descriptor & 0x40002) == 0x40002) {
 			/* supersection descriptor */
 			uint32_t va_range = 16*1024*1024-1; /* 16MB range */
 			uint32_t va_start = pt_idx << 20;
@@ -310,8 +308,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
 				if ((second_lvl_descriptor & 3) == 0) {
 					/* skip entry */
 					pt2_idx++;
-				} else
+				} else if ((second_lvl_descriptor & 3) == 1) {
-				if ((second_lvl_descriptor & 3) == 1) {
 					/* large page */
 					uint32_t va_range = 64*1024-1; /* 64KB range */
 					uint32_t va_start = (pt_idx << 20) + (pt2_idx << 12);

src/target/armv8.c

@@ -1966,7 +1966,7 @@ int armv8_get_gdb_reg_list(struct target *target,
 			*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
 
 			for (i = 0; i < *reg_list_size; i++)
-					(*reg_list)[i] = armv8_reg_current(arm, i);
+				(*reg_list)[i] = armv8_reg_current(arm, i);
 			return ERROR_OK;
 
 		case REG_CLASS_ALL:
@@ -1974,7 +1974,7 @@ int armv8_get_gdb_reg_list(struct target *target,
 			*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
 
 			for (i = 0; i < *reg_list_size; i++)
-					(*reg_list)[i] = armv8_reg_current(arm, i);
+				(*reg_list)[i] = armv8_reg_current(arm, i);
 
 			return ERROR_OK;
 

src/target/cortex_a.c

@@ -1324,21 +1324,21 @@ static int cortex_a_set_breakpoint(struct target *target,
 			brp_list[brp_i].value);
 	} else if (breakpoint->type == BKPT_SOFT) {
 		uint8_t code[4];
-		/* length == 2: Thumb breakpoint */
+		if (breakpoint->length == 2) {
-		if (breakpoint->length == 2)
+			/* length == 2: Thumb breakpoint */
 			buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
-		else
+		} else if (breakpoint->length == 3) {
-		/* length == 3: Thumb-2 breakpoint, actual encoding is
+			/* length == 3: Thumb-2 breakpoint, actual encoding is
-		 * a regular Thumb BKPT instruction but we replace a
+			 * a regular Thumb BKPT instruction but we replace a
-		 * 32bit Thumb-2 instruction, so fix-up the breakpoint
+			 * 32bit Thumb-2 instruction, so fix-up the breakpoint
-		 * length
+			 * length
-		 */
+			 */
-		if (breakpoint->length == 3) {
 			buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
 			breakpoint->length = 4;
-		} else
+		} else {
 			/* length == 4, normal ARM breakpoint */
 			buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
+		}
 
 		retval = target_read_memory(target,
 				breakpoint->address & 0xFFFFFFFE,
@@ -1348,8 +1348,7 @@ static int cortex_a_set_breakpoint(struct target *target,
 			return retval;
 
 		/* make sure data cache is cleaned & invalidated down to PoC */
-		armv7a_cache_flush_virt(target, breakpoint->address,
+		armv7a_cache_flush_virt(target, breakpoint->address, breakpoint->length);
-						breakpoint->length);
 
 		retval = target_write_memory(target,
 				breakpoint->address & 0xFFFFFFFE,
@@ -1358,10 +1357,8 @@ static int cortex_a_set_breakpoint(struct target *target,
 			return retval;
 
 		/* update i-cache at breakpoint location */
-		armv7a_l1_d_cache_inval_virt(target, breakpoint->address,
+		armv7a_l1_d_cache_inval_virt(target, breakpoint->address, breakpoint->length);
-					breakpoint->length);
+		armv7a_l1_i_cache_inval_virt(target, breakpoint->address, breakpoint->length);
-		armv7a_l1_i_cache_inval_virt(target, breakpoint->address,
-						 breakpoint->length);
 
 		breakpoint->is_set = true;
 	}

src/target/mips32.c

@@ -2357,7 +2357,7 @@ COMMAND_HANDLER(mips32_handle_scan_delay_command)
 	if (CMD_ARGC == 1)
 		COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
 	else if (CMD_ARGC > 1)
-			return ERROR_COMMAND_SYNTAX_ERROR;
+		return ERROR_COMMAND_SYNTAX_ERROR;
 
 	command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
 	if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {

src/target/mips_m4k.c

@@ -1397,7 +1397,7 @@ COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
 	if (CMD_ARGC == 1)
 		COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
 	else if (CMD_ARGC > 1)
-			return ERROR_COMMAND_SYNTAX_ERROR;
+		return ERROR_COMMAND_SYNTAX_ERROR;
 
 	command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
 	if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {

src/target/stm8.c

@@ -689,15 +689,13 @@ static int stm8_write_flash(struct target *target, enum mem_type type,
 			if (stm8->flash_ncr2)
 				stm8_write_u8(target, stm8->flash_ncr2, ~(PRG + opt));
 			blocksize = blocksize_param;
-		} else
+		} else if ((bytecnt >= 4) && ((address & 0x3) == 0)) {
-		if ((bytecnt >= 4) && ((address & 0x3) == 0)) {
 			if (stm8->flash_cr2)
 				stm8_write_u8(target, stm8->flash_cr2, WPRG + opt);
 			if (stm8->flash_ncr2)
 				stm8_write_u8(target, stm8->flash_ncr2, ~(WPRG + opt));
 			blocksize = 4;
-		} else
+		} else if (blocksize != 1) {
-		if (blocksize != 1) {
 			if (stm8->flash_cr2)
 				stm8_write_u8(target, stm8->flash_cr2, opt);
 			if (stm8->flash_ncr2)
@@ -1552,8 +1550,8 @@ static int stm8_set_watchpoint(struct target *target,
 	}
 
 	if (watchpoint->length != 1) {
-			LOG_ERROR("Only watchpoints of length 1 are supported");
+		LOG_ERROR("Only watchpoints of length 1 are supported");
-			return ERROR_TARGET_UNALIGNED_ACCESS;
+		return ERROR_TARGET_UNALIGNED_ACCESS;
 	}
 
 	enum hw_break_type enable = 0;

src/xsvf/xsvf.c

@@ -749,10 +749,10 @@ COMMAND_HANDLER(handle_xsvf_command)
 				int delay;
 
 				if (read(xsvf_fd, &wait_local, 1) < 0
-					|| read(xsvf_fd, &end, 1) < 0
+						|| read(xsvf_fd, &end, 1) < 0
-					|| read(xsvf_fd, delay_buf, 4) < 0) {
+						|| read(xsvf_fd, delay_buf, 4) < 0) {
-						do_abort = 1;
+					do_abort = 1;
-						break;
+					break;
 				}
 
 				wait_state = xsvf_to_tap(wait_local);