diff --git a/doc/openocd.texi b/doc/openocd.texi index c30c5bc33..b7512feb5 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -9938,6 +9938,43 @@ A @emph{hart} is a hardware thread. A hart may share resources (eg. FPU) with another hart, or may be a separate core. RISC-V treats those the same, and OpenOCD exposes each hart as a separate core. +@subsection Vector Registers + +For harts that implement the vector extension, OpenOCD provides access to the +relevant CSRs, as well as the vector registers (v0-v31). The size of each +vector register is dependent on the value of vlenb. RISC-V allows each vector +register to be divided into selected-width elements, and this division can be +changed at run-time. Because OpenOCD cannot update register definitions at +run-time, it exposes each vector register to gdb as a union of fields of +vectors so that users can easily access individual bytes, shorts, words, +longs, and quads inside each vector register. It is left to gdb or +higher-level debuggers to present this data in a more intuitive format. + +In the XML register description, the vector registers (when vlenb=16) look as +follows: + +@example + + + + + + + + + + + + + + +... + + +@end example + @subsection RISC-V Debug Configuration Commands @deffn Command {riscv dump_sample_buf} [base64]