From 2fe392ef5085432bb5ae762469ed16e08678f102 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sat, 3 Feb 2024 14:29:57 +0100 Subject: [PATCH] flash: psoc6: drop use of 'coreid' to identify the CPU The flag '-coreid' is used by the command 'target create' to specify the debug controller of the target, either in case of a single debug controller for multiple CPU (e.g. RISC-V harts) or in case of multiple CPU on a DAP access port (e.g. Cortex-A SMP cluster). It is also currently used to specify the CPU ID in a SMP cluster, but this is going to be reworked. This flag has no effects on Cortex-M; ARM specifies that only one CPU Cortex-M can occupy the DAP access port by using hardcoded addresses. The flash driver 'psoc6' uses the flag '-coreid' to detect if the current target is the Cortex-M0 on AP#1 or the Cortex-M4 on AP#2 in the SoC. There are other ways to run such detection, without using such unrelated '-coreid' flag, e.g. using the AP number or the arch type of the target. Use the arch type to detect Cortex-M0 (ARM_ARCH_V6M) vs Cortex-M4 (ARM_ARCH_V7M). Drop the flags '-coreid' from the psoc6 configuration file. Change-Id: I0b9601c160dd4f2421a03ce6e3e7c55c6212f714 Signed-off-by: Antonio Borneo Reviewed-on: https://review.openocd.org/c/openocd/+/8128 Tested-by: jenkins Reviewed-by: Tomas Vanek --- src/flash/nor/psoc6.c | 7 +++++-- tcl/target/psoc6.cfg | 4 ++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/flash/nor/psoc6.c b/src/flash/nor/psoc6.c index 859b3e9ec..47f3ac698 100644 --- a/src/flash/nor/psoc6.c +++ b/src/flash/nor/psoc6.c @@ -223,6 +223,8 @@ static int ipc_poll_lock_stat(struct target *target, uint32_t ipc_id, bool lock_ { int hr; uint32_t reg_val; + struct armv7m_common *armv7m = target_to_armv7m(target); + bool is_cm0 = (armv7m->arm.arch == ARM_ARCH_V6M); struct timeout to; timeout_init(&to, IPC_TIMEOUT_MS); @@ -244,7 +246,7 @@ static int ipc_poll_lock_stat(struct target *target, uint32_t ipc_id, bool lock_ return ERROR_OK; } - if (target->coreid) { + if (!is_cm0) { LOG_WARNING("SROM API calls via CM4 target are supported on single-core PSoC6 devices only. " "Please perform all Flash-related operations via CM0+ target on dual-core devices."); } @@ -886,7 +888,8 @@ static int handle_reset_halt(struct target *target) { int hr; uint32_t reset_addr; - bool is_cm0 = (target->coreid == 0); + struct armv7m_common *armv7m = target_to_armv7m(target); + bool is_cm0 = (armv7m->arm.arch == ARM_ARCH_V6M); /* Halt target device */ if (target->state != TARGET_HALTED) { diff --git a/tcl/target/psoc6.cfg b/tcl/target/psoc6.cfg index d69515cdf..52b04f569 100644 --- a/tcl/target/psoc6.cfg +++ b/tcl/target/psoc6.cfg @@ -113,7 +113,7 @@ proc psoc6_deassert_post { target } { } if { $_ENABLE_CM0 } { - target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 + target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 ${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 ${TARGET}.cm0 @@ -128,7 +128,7 @@ if { $_ENABLE_CM0 } { } if { $_ENABLE_CM4 } { - target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1 + target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 ${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 ${TARGET}.cm4