doc: Minimally describe the BSCAN tunnel interface.
Add minimal documentation for the BSCAN tunnel interface. This is based on Tim Newsome <tim@sifive.com>'s work on the RISC-V fork. Change-Id: I5e0cd6972cb90649670249765e9bb30c2847eea6 Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8297 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
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@ -11279,8 +11279,22 @@ and DBUS registers, respectively.
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@end deffn
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@end deffn
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@deffn {Command} {riscv use_bscan_tunnel} value
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@deffn {Command} {riscv use_bscan_tunnel} value
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Enable or disable use of a BSCAN tunnel to reach DM. Supply the width of
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Enable or disable use of a BSCAN tunnel to reach the Debug Module. Supply the
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the DM transport TAP's instruction register to enable. Supply a value of 0 to disable.
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width of the DM transport TAP's instruction register to enable. Supply a
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value of 0 to disable.
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This BSCAN tunnel interface is specific to SiFive IP. Anybody may implement
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it, but currently there is no good documentation on it. In a nutshell, this
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feature scans USER4 into a Xilinx TAP to select the tunnel device (assuming
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hardware is present and it is hooked up to the Xilinx USER4 IR) and
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encapsulates a tunneled scan directive into a DR scan into the Xilinx TAP. A
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tunneled DR scan consists of:
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@enumerate
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@item 1 bit that selects IR when 0, or DR when 1
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@item 7 bits that encode the width of the desired tunneled scan
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@item A width+1 stream of bits for the tunneled TDI. The plus one is because there is a one-clock skew between TDI of Xilinx chain and TDO from tunneled chain.
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@item 3 bits of zero that the tunnel uses to go back to idle state.
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@end enumerate
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@end deffn
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@end deffn
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@deffn {Command} {riscv set_ebreakm} on|off
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@deffn {Command} {riscv set_ebreakm} on|off
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