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tcl: target: omit apcsw for hla 

When using stlink for CM7 targets we have to rely on its firmware
to do the right thing as direct DAP access is not possible.

Change-Id: Ieee69f4eeea5c911f89f060f31ce86ed043bdfd0
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4732
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Paul Fertser 2018-10-22 23:13:04 +03:00 committed by Tomas Vanek
parent da4b2d5beb
commit 2ed21488cd
3 changed files with 24 additions and 21 deletions
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9
tcl/target/atsamv.cfg
View File

@ -45,10 +45,6 @@ if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to # if srst is not fitted use SYSRESETREQ to
# perform a soft reset # perform a soft reset
cortex_m reset_config sysresetreq cortex_m reset_config sysresetreq
}
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3 # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
@ -57,3 +53,8 @@ flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
# RAM when operating on typical variables, and is generally no worse when # RAM when operating on typical variables, and is generally no worse when
# operating on special memory locations. # operating on special memory locations.
$_CHIPNAME.dap apcsw 0x08000000 0x08000000 $_CHIPNAME.dap apcsw 0x08000000 0x08000000
}
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME

15
tcl/target/stm32f7x.cfg
View File

@ -65,6 +65,14 @@ if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to # if srst is not fitted use SYSRESETREQ to
# perform a soft reset # perform a soft reset
cortex_m reset_config sysresetreq cortex_m reset_config sysresetreq
# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
# makes the data access cacheable. This allows reading and writing data in the
# CPU cache from the debugger, which is far more useful than going straight to
# RAM when operating on typical variables, and is generally no worse when
# operating on special memory locations.
$_CHIPNAME.dap apcsw 0x08000000 0x08000000
} }
$_TARGETNAME configure -event examine-end { $_TARGETNAME configure -event examine-end {
@ -146,10 +154,3 @@ $_TARGETNAME configure -event reset-start {
adapter_khz 2000 adapter_khz 2000
} }
# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
# makes the data access cacheable. This allows reading and writing data in the
# CPU cache from the debugger, which is far more useful than going straight to
# RAM when operating on typical variables, and is generally no worse when
# operating on special memory locations.
$_CHIPNAME.dap apcsw 0x08000000 0x08000000

15
tcl/target/stm32h7x.cfg
View File

@ -63,6 +63,14 @@ if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to # if srst is not fitted use SYSRESETREQ to
# perform a soft reset # perform a soft reset
cortex_m reset_config sysresetreq cortex_m reset_config sysresetreq
# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
# makes the data access cacheable. This allows reading and writing data in the
# CPU cache from the debugger, which is far more useful than going straight to
# RAM when operating on typical variables, and is generally no worse when
# operating on special memory locations.
$_CHIPNAME.dap apcsw 0x08000000 0x08000000
} }
$_TARGETNAME configure -event examine-end { $_TARGETNAME configure -event examine-end {
@ -93,10 +101,3 @@ $_TARGETNAME configure -event reset-init {
adapter_khz 4000 adapter_khz 4000
} }
# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
# makes the data access cacheable. This allows reading and writing data in the
# CPU cache from the debugger, which is far more useful than going straight to
# RAM when operating on typical variables, and is generally no worse when
# operating on special memory locations.
$_CHIPNAME.dap apcsw 0x08000000 0x08000000