Added timeout(instead of infinite loop) to soft_reset_halt
git-svn-id: svn://svn.berlios.de/openocd/trunk@533 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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@ -365,14 +365,28 @@ int arm720t_soft_reset_halt(struct target_s *target)
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
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arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
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arm720t_common_t *arm720t = arm7tdmi->arch_info;
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arm720t_common_t *arm720t = arm7tdmi->arch_info;
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int i;
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reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
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reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
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target->type->halt(target);
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target->type->halt(target);
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while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
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for (i=0; i<10; i++)
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{
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if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
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{
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{
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embeddedice_read_reg(dbg_stat);
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embeddedice_read_reg(dbg_stat);
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jtag_execute_queue();
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jtag_execute_queue();
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} else
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{
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break;
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}
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/* do not eat all CPU, time out after 1 se*/
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usleep(100*1000);
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}
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if (i==10)
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{
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LOG_ERROR("Failed to halt CPU after 1 sec");
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return ERROR_TARGET_TIMEOUT;
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}
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}
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target->state = TARGET_HALTED;
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target->state = TARGET_HALTED;
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@ -622,13 +622,27 @@ int arm920t_soft_reset_halt(struct target_s *target)
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arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
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arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
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arm920t_common_t *arm920t = arm9tdmi->arch_info;
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arm920t_common_t *arm920t = arm9tdmi->arch_info;
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reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
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reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
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int i;
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target->type->halt(target);
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target->type->halt(target);
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while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
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for (i=0; i<10; i++)
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{
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if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
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{
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{
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embeddedice_read_reg(dbg_stat);
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embeddedice_read_reg(dbg_stat);
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jtag_execute_queue();
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jtag_execute_queue();
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} else
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{
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break;
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}
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/* do not eat all CPU, time out after 1 se*/
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usleep(100*1000);
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}
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if (i==10)
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{
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LOG_ERROR("Failed to halt CPU after 1 sec");
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return ERROR_TARGET_TIMEOUT;
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}
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}
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target->state = TARGET_HALTED;
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target->state = TARGET_HALTED;
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@ -578,13 +578,27 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
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arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
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arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
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arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
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arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
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reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
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reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
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int i;
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target->type->halt(target);
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target->type->halt(target);
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while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
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for (i=0; i<10; i++)
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{
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if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
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{
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{
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embeddedice_read_reg(dbg_stat);
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embeddedice_read_reg(dbg_stat);
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jtag_execute_queue();
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jtag_execute_queue();
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} else
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{
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break;
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}
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/* do not eat all CPU, time out after 1 se*/
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usleep(100*1000);
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}
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if (i==10)
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{
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LOG_ERROR("Failed to halt CPU after 1 sec");
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return ERROR_TARGET_TIMEOUT;
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}
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}
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target->state = TARGET_HALTED;
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target->state = TARGET_HALTED;
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