src/target/riscv: fix compile issue due to memory access and parse range api changes

see #1162 and #1167

Change-Id: I02ab8eb7557b92cc1ff36b087b37e58abdc5011c
Signed-off-by: Huaqi Fang <578567190@qq.com>

src/target/riscv/nuclei_riscv.c

@@ -850,7 +850,7 @@ COMMAND_HANDLER(nuclei_set_expose_cpu_core)
 	int ret = ERROR_OK;
 
 	for (unsigned int i = 0; i < CMD_ARGC; i++) {
-		ret = parse_ranges(&info->expose_nuclei_cpu_core, CMD_ARGV[i], "nuclei_cpu_core", 0xFF);
+		ret = parse_reg_ranges(&info->expose_nuclei_cpu_core, CMD_ARGV[i], "nuclei_cpu_core", 0xFF);
 		if (ret != ERROR_OK)
 			break;
 	}

src/target/riscv/nuclei_riscv.h

@@ -8,6 +8,9 @@
 #ifndef TARGET__RISCV__NUCLEI_RISCV_H
 #define TARGET__RISCV__NUCLEI_RISCV_H
 
+#include <stdint.h>
+
 extern const struct command_registration nuclei_command_group_handlers[];
+extern uint64_t nuclei_get_dmcustom(struct target *target, uint32_t type, uint32_t hart_id, uint32_t index);
 
 #endif /* TARGET__RISCV__NUCLEI_RISCV_H */

src/target/riscv/riscv-013.c

@@ -35,6 +35,7 @@
 #include "batch.h"
 #include "debug_reg_printer.h"
 #include "field_helpers.h"
+#include "nuclei_riscv.h"
 
 static int riscv013_on_step_or_resume(struct target *target, bool step);
 static int riscv013_step_or_resume_current_hart(struct target *target,
@@ -2343,7 +2344,14 @@ int riscv013_get_register_buf(struct target *target, uint8_t *value,
 		result = riscv_program_exec(&program, target);
 		if (result != ERROR_OK)
 			LOG_TARGET_ERROR(target, "Failed to execute vse while read");
-		read_memory(target, algorithm_v->address, 1, riscv_vlenb(target), value, 1);
+		const riscv_mem_access_args_t args = {
+				.address = algorithm_v->address,
+				.read_buffer = value,
+				.size = 1,
+				.count = riscv_vlenb(target),
+				.increment = 1,
+			};
+		read_memory(target, args);
 
 		target_free_working_area(target, algorithm_v);
 	}
@@ -2400,9 +2408,15 @@ int riscv013_set_register_buf(struct target *target, enum gdb_regno regno,
 		if (result != ERROR_OK)
 			LOG_TARGET_ERROR(target, "Failed to alloc workarea while write");
 		register_write_direct(target, GDB_REGNO_S0, algorithm_v->address);
-		write_memory(target, algorithm_v->address, 1, riscv_vlenb(target), value);
+		const riscv_mem_access_args_t args = {
+				.address = algorithm_v->address,
+				.write_buffer = value,
+				.size = 1,
+				.count = riscv_vlenb(target),
+				.increment = 1,
+			};
+		write_memory(target, args);
 
-		struct riscv_program program;
 		riscv_program_init(&program, target);
 		if (debug_vsew == 32)
 			riscv_program_insert(&program, vle32_v(S0, vnum));

src/target/riscv/riscv.c

@@ -3276,9 +3276,9 @@ static int riscv_rw_memory(struct target *target, const riscv_mem_access_args_t
 		r->num_enabled_mem_access_methods = 1;
 		r->mem_access_methods[0] = RISCV_MEM_ACCESS_SYSBUS;
 		if (is_write)
-			retval = tt->write_memory(target, address, size, count, write_buffer);
+			retval = r->write_memory(target, args);
 		else
-			retval = r->read_memory(target, address, size, count, read_buffer, size);
+			retval = r->read_memory(target, args);
 		r->num_enabled_mem_access_methods = oldcnt;
 		r->mem_access_methods[0] = oldmethod;
 		return retval;
@@ -4338,7 +4338,7 @@ static int parse_reg_ranges_impl(struct list_head *ranges, char *args,
 	return ERROR_OK;
 }
 
-static int parse_reg_ranges(struct list_head *ranges, const char *tcl_arg,
+int parse_reg_ranges(struct list_head *ranges, const char *tcl_arg,
 		const char *reg_type, unsigned int max_val)
 {
 	char *args = strdup(tcl_arg);

src/target/riscv/riscv.h

@@ -489,4 +489,7 @@ int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32
 int riscv_interrupts_disable(struct target *target, uint64_t ie_mask, uint64_t *old_mstatus);
 int riscv_interrupts_restore(struct target *target, uint64_t old_mstatus);
 
+int parse_reg_ranges(struct list_head *ranges, const char *tcl_arg,
+		const char *reg_type, unsigned int max_val);
+
 #endif /* OPENOCD_TARGET_RISCV_RISCV_H */