From 28c24a5c41c47a66e9310912f88148814f730a25 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sat, 3 Jul 2021 16:47:35 +0200 Subject: [PATCH] openocd: fix simple cases of Yoda condition There are ~900 Yoda conditions to be aligned to the coding style. For recurrent Yoda conditions it's preferable using a trivial script in order to minimize the review effort. E.g. comparison of uppercase macro/enum with lowercase variable: - ...(ERROR_OK == retval)... + ...(retval == ERROR_OK)... Patch generated automatically with the command: sed -i \ 's/(\([A-Z][A-Z0-9_]*\) \([=!]=\) \([a-z][a-z0-9_]*\))/(\3 \2 \1)/g' \ $(find src/ -type f) While there, remove the braces {} around a single statement block to prevent warning from checkpatch. Change-Id: If585b0a4b4578879c87b2dd74d9e0025e275ec6b Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6354 Tested-by: jenkins Reviewed-by: Xiang W --- src/flash/common.c | 2 +- src/flash/nand/at91sam9.c | 14 +- src/flash/nand/core.c | 18 +-- src/flash/nand/driver.c | 2 +- src/flash/nand/fileio.c | 8 +- src/flash/nand/lpc3180.c | 4 +- src/flash/nand/lpc32xx.c | 182 ++++++++++++------------- src/flash/nand/s3c24xx.h | 2 +- src/flash/nand/tcl.c | 28 ++-- src/flash/nor/ambiqmicro.c | 4 +- src/flash/nor/atsamv.c | 2 +- src/flash/nor/avrf.c | 2 +- src/flash/nor/cc26xx.c | 38 +++--- src/flash/nor/cc3220sf.c | 44 +++--- src/flash/nor/efm32.c | 76 +++++------ src/flash/nor/em357.c | 6 +- src/flash/nor/fm3.c | 2 +- src/flash/nor/lpc2000.c | 2 +- src/flash/nor/lpc2900.c | 12 +- src/flash/nor/max32xxx.c | 10 +- src/flash/nor/msp432.c | 78 +++++------ src/flash/nor/pic32mx.c | 4 +- src/flash/nor/psoc4.c | 4 +- src/flash/nor/sim3x.c | 2 +- src/flash/nor/stellaris.c | 2 +- src/flash/nor/stm32f1x.c | 26 ++-- src/flash/nor/stm32f2x.c | 20 +-- src/flash/nor/stm32h7x.c | 12 +- src/flash/nor/stm32l4x.c | 22 +-- src/flash/nor/stm32lx.c | 6 +- src/flash/nor/stmqspi.c | 6 +- src/flash/nor/str7x.c | 2 +- src/flash/nor/str9x.c | 2 +- src/flash/nor/str9xpec.c | 22 +-- src/flash/nor/swm050.c | 2 +- src/flash/nor/tcl.c | 24 ++-- src/flash/nor/xcf.c | 22 +-- src/hello.c | 2 +- src/helper/command.c | 12 +- src/helper/command.h | 4 +- src/helper/fileio.c | 2 +- src/jtag/adapter.c | 6 +- src/jtag/aice/aice_transport.c | 2 +- src/jtag/aice/aice_usb.c | 168 +++++++++++------------ src/jtag/core.c | 18 +-- src/jtag/drivers/parport.c | 2 +- src/jtag/drivers/versaloon/versaloon.c | 2 +- src/jtag/drivers/vsllink.c | 4 +- src/jtag/drivers/xds110.c | 10 +- src/jtag/hla/hla_tcl.c | 2 +- src/jtag/tcl.c | 10 +- src/openocd.c | 16 +-- src/pld/pld.c | 4 +- src/rtos/rtos.c | 2 +- src/server/gdb_server.c | 4 +- src/server/server.c | 6 +- src/svf/svf.c | 13 +- src/target/arc.c | 8 +- src/target/arc_mem.c | 2 +- src/target/arm_cti.c | 4 +- src/target/arm_dap.c | 2 +- src/target/arm_tpiu_swo.c | 18 +-- src/target/armv8.c | 2 +- src/target/cortex_a.c | 6 +- src/target/etm.c | 2 +- src/target/mips_m4k.c | 4 +- src/target/mips_mips64.c | 2 +- src/target/nds32.c | 14 +- src/target/nds32_v2.c | 20 +-- src/target/nds32_v3.c | 2 +- src/target/nds32_v3_common.c | 8 +- src/target/nds32_v3m.c | 2 +- src/target/openrisc/jsp_server.c | 4 +- src/target/smp.c | 2 +- src/target/target.c | 44 +++--- src/target/x86_32_common.c | 2 +- 76 files changed, 575 insertions(+), 576 deletions(-) diff --git a/src/flash/common.c b/src/flash/common.c index 3e2551192..e8e795a4e 100644 --- a/src/flash/common.c +++ b/src/flash/common.c @@ -32,7 +32,7 @@ unsigned get_flash_name_index(const char *name) unsigned requested; int retval = parse_uint(name_index + 1, &requested); /* detect parsing error by forcing past end of bank list */ - return (ERROR_OK == retval) ? requested : ~0U; + return (retval == ERROR_OK) ? requested : ~0U; } bool flash_driver_name_matches(const char *name, const char *expected) diff --git a/src/flash/nand/at91sam9.c b/src/flash/nand/at91sam9.c index 534f20ede..4341935fe 100644 --- a/src/flash/nand/at91sam9.c +++ b/src/flash/nand/at91sam9.c @@ -368,16 +368,16 @@ static int at91sam9_read_page(struct nand_device *nand, uint32_t page, uint32_t status; retval = at91sam9_ecc_init(target, info); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = nand_page_command(nand, page, NAND_CMD_READ0, !data); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (data) { retval = nand_read_data_page(nand, data, data_size); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; } @@ -443,16 +443,16 @@ static int at91sam9_write_page(struct nand_device *nand, uint32_t page, uint32_t parity, nparity; retval = at91sam9_ecc_init(target, info); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (data) { retval = nand_write_data_page(nand, data, data_size); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Unable to write data to NAND device"); return retval; } @@ -476,7 +476,7 @@ static int at91sam9_write_page(struct nand_device *nand, uint32_t page, if (!oob) free(oob_data); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Unable to write OOB data to NAND"); return retval; } diff --git a/src/flash/nand/core.c b/src/flash/nand/core.c index baef5d59c..8e2af2338 100644 --- a/src/flash/nand/core.c +++ b/src/flash/nand/core.c @@ -750,7 +750,7 @@ int nand_page_command(struct nand_device *nand, uint32_t page, nand->controller->address(nand, (page >> 16) & 0xff); /* large page devices need a start command if reading */ - if (NAND_CMD_READ0 == cmd) + if (cmd == NAND_CMD_READ0) nand->controller->command(nand, NAND_CMD_READSTART); } @@ -772,7 +772,7 @@ int nand_read_data_page(struct nand_device *nand, uint8_t *data, uint32_t size) if (nand->controller->read_block_data != NULL) retval = (nand->controller->read_block_data)(nand, data, size); - if (ERROR_NAND_NO_BUFFER == retval) { + if (retval == ERROR_NAND_NO_BUFFER) { uint32_t i; int incr = (nand->device->options & NAND_BUSWIDTH_16) ? 2 : 1; @@ -793,7 +793,7 @@ int nand_read_page_raw(struct nand_device *nand, uint32_t page, int retval; retval = nand_page_command(nand, page, NAND_CMD_READ0, !data); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (data) @@ -812,7 +812,7 @@ int nand_write_data_page(struct nand_device *nand, uint8_t *data, uint32_t size) if (nand->controller->write_block_data != NULL) retval = (nand->controller->write_block_data)(nand, data, size); - if (ERROR_NAND_NO_BUFFER == retval) { + if (retval == ERROR_NAND_NO_BUFFER) { bool is16bit = nand->device->options & NAND_BUSWIDTH_16; uint32_t incr = is16bit ? 2 : 1; uint16_t write_data; @@ -825,7 +825,7 @@ int nand_write_data_page(struct nand_device *nand, uint8_t *data, uint32_t size) write_data = *data; retval = nand->controller->write_data(nand, write_data); - if (ERROR_OK != retval) + if (retval != ERROR_OK) break; data += incr; @@ -849,7 +849,7 @@ int nand_write_finish(struct nand_device *nand) return ERROR_NAND_OPERATION_TIMEOUT; retval = nand_read_status(nand, &status); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("couldn't read status"); return ERROR_NAND_OPERATION_FAILED; } @@ -870,12 +870,12 @@ int nand_write_page_raw(struct nand_device *nand, uint32_t page, int retval; retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (data) { retval = nand_write_data_page(nand, data, data_size); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Unable to write data to NAND device"); return retval; } @@ -883,7 +883,7 @@ int nand_write_page_raw(struct nand_device *nand, uint32_t page, if (oob) { retval = nand_write_data_page(nand, oob, oob_size); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Unable to write OOB data to NAND device"); return retval; } diff --git a/src/flash/nand/driver.c b/src/flash/nand/driver.c index f7665603f..b525f3d0a 100644 --- a/src/flash/nand/driver.c +++ b/src/flash/nand/driver.c @@ -75,7 +75,7 @@ int nand_driver_walk(nand_driver_walker_t f, void *x) { for (unsigned i = 0; nand_flash_controllers[i]; i++) { int retval = (*f)(nand_flash_controllers[i], x); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; } return ERROR_OK; diff --git a/src/flash/nand/fileio.c b/src/flash/nand/fileio.c index fee401292..5504841b5 100644 --- a/src/flash/nand/fileio.c +++ b/src/flash/nand/fileio.c @@ -67,8 +67,8 @@ int nand_fileio_start(struct command_invocation *cmd, if (NULL != filename) { int retval = fileio_open(&state->fileio, filename, filemode, FILEIO_BINARY); - if (ERROR_OK != retval) { - const char *msg = (FILEIO_READ == filemode) ? "read" : "write"; + if (retval != ERROR_OK) { + const char *msg = (filemode == FILEIO_READ) ? "read" : "write"; command_print(cmd, "failed to open '%s' for %s access", filename, msg); return retval; @@ -124,7 +124,7 @@ COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state, struct nand_device *nand; int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (NULL == nand->device) { @@ -159,7 +159,7 @@ COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state, } retval = nand_fileio_start(CMD, nand, CMD_ARGV[1], filemode, state); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (!need_size) { diff --git a/src/flash/nand/lpc3180.c b/src/flash/nand/lpc3180.c index 6ce05753e..bda7b87c3 100644 --- a/src/flash/nand/lpc3180.c +++ b/src/flash/nand/lpc3180.c @@ -589,7 +589,7 @@ static int lpc3180_write_page(struct nand_device *nand, oob_size); } retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* allocate a working area */ @@ -970,7 +970,7 @@ static int lpc3180_read_page(struct nand_device *nand, /* read always the data and also oob areas*/ retval = nand_page_command(nand, page, NAND_CMD_READ0, 0); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* allocate a working area */ diff --git a/src/flash/nand/lpc32xx.c b/src/flash/nand/lpc32xx.c index 3e2add49b..49890c2ab 100644 --- a/src/flash/nand/lpc32xx.c +++ b/src/flash/nand/lpc32xx.c @@ -141,7 +141,7 @@ static float lpc32xx_cycle_time(struct nand_device *nand) /* determine current SYSCLK (13'MHz or main oscillator) */ retval = target_read_u32(target, 0x40004050, &sysclk_ctrl); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not read SYSCLK_CTRL"); return ERROR_NAND_OPERATION_FAILED; } @@ -153,7 +153,7 @@ static float lpc32xx_cycle_time(struct nand_device *nand) /* determine selected HCLK source */ retval = target_read_u32(target, 0x40004044, &pwr_ctrl); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not read HCLK_CTRL"); return ERROR_NAND_OPERATION_FAILED; } @@ -162,14 +162,14 @@ static float lpc32xx_cycle_time(struct nand_device *nand) hclk = sysclk; else { retval = target_read_u32(target, 0x40004058, &hclkpll_ctrl); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not read HCLKPLL_CTRL"); return ERROR_NAND_OPERATION_FAILED; } hclk_pll = lpc32xx_pll(sysclk, hclkpll_ctrl); retval = target_read_u32(target, 0x40004040, &hclkdiv_ctrl); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not read CLKDIV_CTRL"); return ERROR_NAND_OPERATION_FAILED; } @@ -235,21 +235,21 @@ static int lpc32xx_init(struct nand_device *nand) /* FLASHCLK_CTRL = 0x22 (enable clk for MLC) */ retval = target_write_u32(target, 0x400040c8, 0x22); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set FLASHCLK_CTRL"); return ERROR_NAND_OPERATION_FAILED; } /* MLC_CEH = 0x0 (Force nCE assert) */ retval = target_write_u32(target, 0x200b804c, 0x0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_CEH"); return ERROR_NAND_OPERATION_FAILED; } /* MLC_LOCK = 0xa25e (unlock protected registers) */ retval = target_write_u32(target, 0x200b8044, 0xa25e); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_LOCK"); return ERROR_NAND_OPERATION_FAILED; } @@ -264,7 +264,7 @@ static int lpc32xx_init(struct nand_device *nand) if (bus_width == 16) mlc_icr_value |= 0x1; retval = target_write_u32(target, 0x200b8030, mlc_icr_value); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ICR"); return ERROR_NAND_OPERATION_FAILED; } @@ -282,7 +282,7 @@ static int lpc32xx_init(struct nand_device *nand) /* MLC_LOCK = 0xa25e (unlock protected registers) */ retval = target_write_u32(target, 0x200b8044, 0xa25e); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_LOCK"); return ERROR_NAND_OPERATION_FAILED; } @@ -296,13 +296,13 @@ static int lpc32xx_init(struct nand_device *nand) | ((trhz & 0x7) << 16) | ((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24)); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_TIME_REG"); return ERROR_NAND_OPERATION_FAILED; } retval = lpc32xx_reset(nand); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return ERROR_NAND_OPERATION_FAILED; } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) { float cycle; @@ -311,7 +311,7 @@ static int lpc32xx_init(struct nand_device *nand) /* FLASHCLK_CTRL = 0x05 (enable clk for SLC) */ retval = target_write_u32(target, 0x400040c8, 0x05); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set FLASHCLK_CTRL"); return ERROR_NAND_OPERATION_FAILED; } @@ -320,7 +320,7 @@ static int lpc32xx_init(struct nand_device *nand) * so reset calling is here at the beginning */ retval = lpc32xx_reset(nand); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return ERROR_NAND_OPERATION_FAILED; /* SLC_CFG = @@ -333,14 +333,14 @@ static int lpc32xx_init(struct nand_device *nand) */ retval = target_write_u32(target, 0x20020014, 0x3e | ((bus_width == 16) ? 1 : 0)); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set SLC_CFG"); return ERROR_NAND_OPERATION_FAILED; } /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */ retval = target_write_u32(target, 0x20020020, 0x03); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set SLC_IEN"); return ERROR_NAND_OPERATION_FAILED; } @@ -349,14 +349,14 @@ static int lpc32xx_init(struct nand_device *nand) /* DMACLK_CTRL = 0x01 (enable clock for DMA controller) */ retval = target_write_u32(target, 0x400040e8, 0x01); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set DMACLK_CTRL"); return ERROR_NAND_OPERATION_FAILED; } /* DMACConfig = DMA enabled*/ retval = target_write_u32(target, 0x31000030, 0x01); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set DMACConfig"); return ERROR_NAND_OPERATION_FAILED; } @@ -380,7 +380,7 @@ static int lpc32xx_init(struct nand_device *nand) | ((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28)); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set SLC_TAC"); return ERROR_NAND_OPERATION_FAILED; } @@ -407,7 +407,7 @@ static int lpc32xx_reset(struct nand_device *nand) } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) { /* MLC_CMD = 0xff (reset controller and NAND device) */ retval = target_write_u32(target, 0x200b8000, 0xff); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_CMD"); return ERROR_NAND_OPERATION_FAILED; } @@ -420,7 +420,7 @@ static int lpc32xx_reset(struct nand_device *nand) } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) { /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */ retval = target_write_u32(target, 0x20020010, 0x6); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set SLC_CTRL"); return ERROR_NAND_OPERATION_FAILED; } @@ -453,14 +453,14 @@ static int lpc32xx_command(struct nand_device *nand, uint8_t command) } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) { /* MLC_CMD = command */ retval = target_write_u32(target, 0x200b8000, command); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_CMD"); return ERROR_NAND_OPERATION_FAILED; } } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) { /* SLC_CMD = command */ retval = target_write_u32(target, 0x20020008, command); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set SLC_CMD"); return ERROR_NAND_OPERATION_FAILED; } @@ -487,14 +487,14 @@ static int lpc32xx_address(struct nand_device *nand, uint8_t address) } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) { /* MLC_ADDR = address */ retval = target_write_u32(target, 0x200b8004, address); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) { /* SLC_ADDR = address */ retval = target_write_u32(target, 0x20020004, address); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set SLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } @@ -521,14 +521,14 @@ static int lpc32xx_write_data(struct nand_device *nand, uint16_t data) } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) { /* MLC_DATA = data */ retval = target_write_u32(target, 0x200b0000, data); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_DATA"); return ERROR_NAND_OPERATION_FAILED; } } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) { /* SLC_DATA = data */ retval = target_write_u32(target, 0x20020000, data); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set SLC_DATA"); return ERROR_NAND_OPERATION_FAILED; } @@ -561,7 +561,7 @@ static int lpc32xx_read_data(struct nand_device *nand, void *data) LOG_ERROR("BUG: bus_width neither 8 nor 16 bit"); return ERROR_NAND_OPERATION_FAILED; } - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not read MLC_DATA"); return ERROR_NAND_OPERATION_FAILED; } @@ -570,7 +570,7 @@ static int lpc32xx_read_data(struct nand_device *nand, void *data) /* data = SLC_DATA, must use 32-bit access */ retval = target_read_u32(target, 0x20020000, &data32); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not read SLC_DATA"); return ERROR_NAND_OPERATION_FAILED; } @@ -600,7 +600,7 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page, /* MLC_CMD = sequential input */ retval = target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_CMD"); return ERROR_NAND_OPERATION_FAILED; } @@ -608,20 +608,20 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page, if (nand->page_size == 512) { /* MLC_ADDR = 0x0 (one column cycle) */ retval = target_write_u32(target, 0x200b8004, 0x0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } /* MLC_ADDR = row */ retval = target_write_u32(target, 0x200b8004, page & 0xff); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } retval = target_write_u32(target, 0x200b8004, (page >> 8) & 0xff); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } @@ -629,7 +629,7 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page, if (nand->address_cycles == 4) { retval = target_write_u32(target, 0x200b8004, (page >> 16) & 0xff); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } @@ -637,25 +637,25 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page, } else { /* MLC_ADDR = 0x0 (two column cycles) */ retval = target_write_u32(target, 0x200b8004, 0x0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } retval = target_write_u32(target, 0x200b8004, 0x0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } /* MLC_ADDR = row */ retval = target_write_u32(target, 0x200b8004, page & 0xff); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } retval = target_write_u32(target, 0x200b8004, (page >> 8) & 0xff); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } @@ -687,27 +687,27 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page, /* write MLC_ECC_ENC_REG to start encode cycle */ retval = target_write_u32(target, 0x200b8008, 0x0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ECC_ENC_REG"); return ERROR_NAND_OPERATION_FAILED; } retval = target_write_memory(target, 0x200a8000, 4, 128, page_buffer); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_BUF (data)"); return ERROR_NAND_OPERATION_FAILED; } retval = target_write_memory(target, 0x200a8000, 1, 6, oob_buffer); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_BUF (oob)"); return ERROR_NAND_OPERATION_FAILED; } /* write MLC_ECC_AUTO_ENC_REG to start auto encode */ retval = target_write_u32(target, 0x200b8010, 0x0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ECC_AUTO_ENC_REG"); return ERROR_NAND_OPERATION_FAILED; } @@ -721,7 +721,7 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page, /* MLC_CMD = auto program command */ retval = target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_CMD"); return ERROR_NAND_OPERATION_FAILED; } @@ -901,14 +901,14 @@ static int lpc32xx_start_slc_dma(struct nand_device *nand, uint32_t count, /* DMACIntTCClear = ch0 */ retval = target_write_u32(target, 0x31000008, 1); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not set DMACIntTCClear"); return retval; } /* DMACIntErrClear = ch0 */ retval = target_write_u32(target, 0x31000010, 1); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not set DMACIntErrClear"); return retval; } @@ -926,28 +926,28 @@ static int lpc32xx_start_slc_dma(struct nand_device *nand, uint32_t count, retval = target_write_u32(target, 0x31000110, 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not set DMACC0Config"); return retval; } /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */ retval = target_write_u32(target, 0x20020010, 0x3); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not set SLC_CTRL"); return retval; } /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/ retval = target_write_u32(target, 0x20020028, 2); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not set SLC_ICR"); return retval; } /* SLC_TC */ retval = target_write_u32(target, 0x20020030, count); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("lpc32xx_start_slc_dma: Could not set SLC_TC"); return retval; } @@ -974,13 +974,13 @@ static int lpc32xx_dma_ready(struct nand_device *nand, int timeout) /* Read DMACRawIntTCStat */ retval = target_read_u32(target, 0x31000014, &tc_stat); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not read DMACRawIntTCStat"); return 0; } /* Read DMACRawIntErrStat */ retval = target_read_u32(target, 0x31000018, &err_stat); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not read DMACRawIntErrStat"); return 0; } @@ -1065,13 +1065,13 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, retval = target_write_memory(target, target_mem_base, 4, nll * sizeof(struct dmac_ll) / 4, (uint8_t *)dmalist); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not write DMA descriptors to IRAM"); return retval; } retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("NAND_CMD_SEQIN failed"); return retval; } @@ -1085,7 +1085,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, WIDTH = bus_width */ retval = target_write_u32(target, 0x20020014, 0x3c); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not set SLC_CFG"); return retval; } @@ -1097,7 +1097,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, retval = target_write_memory(target, target_mem_base + DATA_OFFS, 4, nand->page_size/4, fdata); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not write data to IRAM"); return retval; } @@ -1106,7 +1106,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, retval = target_write_memory(target, 0x31000100, 4, sizeof(struct dmac_ll) / 4, (uint8_t *)dmalist); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not write DMA descriptor to DMAC"); return retval; } @@ -1115,7 +1115,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, int tot_size = nand->page_size; tot_size += tot_size == 2048 ? 64 : 16; retval = lpc32xx_start_slc_dma(nand, tot_size, 0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("DMA failed"); return retval; } @@ -1139,7 +1139,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, static uint32_t hw_ecc[8]; retval = target_read_memory(target, target_mem_base + ECC_OFFS, 4, ecc_count, (uint8_t *)hw_ecc); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Reading hw generated ECC from IRAM failed"); return retval; } @@ -1154,7 +1154,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, } retval = target_write_memory(target, target_mem_base + SPARE_OFFS, 4, foob_size / 4, foob); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Writing OOB to IRAM failed"); return retval; } @@ -1163,7 +1163,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, retval = target_write_memory(target, 0x31000100, 4, sizeof(struct dmac_ll) / 4, (uint8_t *)(&dmalist[nll-1])); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not write OOB DMA descriptor to DMAC"); return retval; } @@ -1173,7 +1173,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, /* DMACIntTCClear = ch0 */ retval = target_write_u32(target, 0x31000008, 1); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not set DMACIntTCClear"); return retval; } @@ -1190,7 +1190,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, retval = target_write_u32(target, 0x31000110, 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not set DMACC0Config"); return retval; } @@ -1203,7 +1203,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, } else { /* Start xfer of data from iram to flash using DMA */ retval = lpc32xx_start_slc_dma(nand, foob_size, 1); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("DMA OOB failed"); return retval; } @@ -1211,7 +1211,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, /* Let NAND start actual writing */ retval = nand_write_finish(nand); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("nand_write_finish failed"); return retval; } @@ -1307,7 +1307,7 @@ static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page, /* MLC_CMD = Read0 */ retval = target_write_u32(target, 0x200b8000, NAND_CMD_READ0); } - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_CMD"); return ERROR_NAND_OPERATION_FAILED; } @@ -1315,20 +1315,20 @@ static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page, /* small page device * MLC_ADDR = 0x0 (one column cycle) */ retval = target_write_u32(target, 0x200b8004, 0x0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } /* MLC_ADDR = row */ retval = target_write_u32(target, 0x200b8004, page & 0xff); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } retval = target_write_u32(target, 0x200b8004, (page >> 8) & 0xff); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } @@ -1336,7 +1336,7 @@ static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page, if (nand->address_cycles == 4) { retval = target_write_u32(target, 0x200b8004, (page >> 16) & 0xff); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } @@ -1345,25 +1345,25 @@ static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page, /* large page device * MLC_ADDR = 0x0 (two column cycles) */ retval = target_write_u32(target, 0x200b8004, 0x0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } retval = target_write_u32(target, 0x200b8004, 0x0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } /* MLC_ADDR = row */ retval = target_write_u32(target, 0x200b8004, page & 0xff); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } retval = target_write_u32(target, 0x200b8004, (page >> 8) & 0xff); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ADDR"); return ERROR_NAND_OPERATION_FAILED; } @@ -1371,7 +1371,7 @@ static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page, /* MLC_CMD = Read Start */ retval = target_write_u32(target, 0x200b8000, NAND_CMD_READSTART); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_CMD"); return ERROR_NAND_OPERATION_FAILED; } @@ -1380,7 +1380,7 @@ static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page, while (page_bytes_done < (uint32_t)nand->page_size) { /* MLC_ECC_AUTO_DEC_REG = dummy */ retval = target_write_u32(target, 0x200b8014, 0xaa55aa55); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_ECC_AUTO_DEC_REG"); return ERROR_NAND_OPERATION_FAILED; } @@ -1392,7 +1392,7 @@ static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page, } retval = target_read_u32(target, 0x200b8048, &mlc_isr); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not read MLC_ISR"); return ERROR_NAND_OPERATION_FAILED; } @@ -1411,7 +1411,7 @@ static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page, if (data) { retval = target_read_memory(target, 0x200a8000, 4, 128, page_buffer + page_bytes_done); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not read MLC_BUF (data)"); return ERROR_NAND_OPERATION_FAILED; } @@ -1420,7 +1420,7 @@ static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page, if (oob) { retval = target_read_memory(target, 0x200a8000, 4, 4, oob_buffer + oob_bytes_done); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not read MLC_BUF (oob)"); return ERROR_NAND_OPERATION_FAILED; } @@ -1462,13 +1462,13 @@ static int lpc32xx_read_page_slc(struct nand_device *nand, retval = target_write_memory(target, target_mem_base, 4, nll * sizeof(struct dmac_ll) / 4, (uint8_t *)dmalist); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not write DMA descriptors to IRAM"); return retval; } retval = nand_page_command(nand, page, NAND_CMD_READ0, 0); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("lpc32xx_read_page_slc: NAND_CMD_READ0 failed"); return retval; } @@ -1482,7 +1482,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand, WIDTH = bus_width */ retval = target_write_u32(target, 0x20020014, 0x3e); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("lpc32xx_read_page_slc: Could not set SLC_CFG"); return retval; } @@ -1490,7 +1490,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand, /* Write first descriptor to DMA controller */ retval = target_write_memory(target, 0x31000100, 4, sizeof(struct dmac_ll) / 4, (uint8_t *)dmalist); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not write DMA descriptor to DMAC"); return retval; } @@ -1499,7 +1499,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand, int tot_size = nand->page_size; tot_size += nand->page_size == 2048 ? 64 : 16; retval = lpc32xx_start_slc_dma(nand, tot_size, 1); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("lpc32xx_read_page_slc: DMA read failed"); return retval; } @@ -1508,7 +1508,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand, if (data) { retval = target_read_memory(target, target_mem_base + DATA_OFFS, 4, data_size/4, data); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not read data from IRAM"); return retval; } @@ -1518,7 +1518,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand, retval = target_read_memory(target, target_mem_base + SPARE_OFFS, 4, oob_size/4, oob); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not read OOB from IRAM"); return retval; } @@ -1530,7 +1530,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand, retval = target_read_memory(target, target_mem_base + SPARE_OFFS, 4, nand->page_size == 2048 ? 16 : 4, foob); lpc32xx_dump_oob(foob, nand->page_size == 2048 ? 64 : 16); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not read OOB from IRAM"); return retval; } @@ -1539,7 +1539,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand, static uint32_t hw_ecc[8]; /* max size */ retval = target_read_memory(target, target_mem_base + ECC_OFFS, 4, ecc_count, (uint8_t *)hw_ecc); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not read hw generated ECC from IRAM"); return retval; } @@ -1633,7 +1633,7 @@ static int lpc32xx_controller_ready(struct nand_device *nand, int timeout) /* Read MLC_ISR, wait for controller to become ready */ retval = target_read_u8(target, 0x200b8048, &status); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set MLC_STAT"); return ERROR_NAND_OPERATION_FAILED; } @@ -1648,7 +1648,7 @@ static int lpc32xx_controller_ready(struct nand_device *nand, int timeout) /* Read SLC_STAT and check READY bit */ retval = target_read_u32(target, 0x20020018, &status); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not set SLC_STAT"); return ERROR_NAND_OPERATION_FAILED; } @@ -1687,7 +1687,7 @@ static int lpc32xx_nand_ready(struct nand_device *nand, int timeout) /* Read MLC_ISR, wait for NAND flash device to * become ready */ retval = target_read_u8(target, 0x200b8048, &status); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not read MLC_ISR"); return ERROR_NAND_OPERATION_FAILED; } @@ -1702,7 +1702,7 @@ static int lpc32xx_nand_ready(struct nand_device *nand, int timeout) /* Read SLC_STAT and check READY bit */ retval = target_read_u32(target, 0x20020018, &status); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("could not read SLC_STAT"); return ERROR_NAND_OPERATION_FAILED; } @@ -1731,7 +1731,7 @@ static int lpc32xx_tc_ready(struct nand_device *nand, int timeout) int retval; /* Read SLC_INT_STAT and check INT_TC_STAT bit */ retval = target_read_u32(target, 0x2002001c, &status); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Could not read SLC_INT_STAT"); return 0; } diff --git a/src/flash/nand/s3c24xx.h b/src/flash/nand/s3c24xx.h index 5c7782dab..4b0c02fc4 100644 --- a/src/flash/nand/s3c24xx.h +++ b/src/flash/nand/s3c24xx.h @@ -51,7 +51,7 @@ S3C24XX_DEVICE_COMMAND(); #define CALL_S3C24XX_DEVICE_COMMAND(d, i) \ do { \ int retval = CALL_COMMAND_HANDLER(s3c24xx_nand_device_command, d, i); \ - if (ERROR_OK != retval) \ + if (retval != ERROR_OK) \ return retval; \ } while (0) diff --git a/src/flash/nand/tcl.c b/src/flash/nand/tcl.c index 9e0ca41ac..cbc51b8d1 100644 --- a/src/flash/nand/tcl.c +++ b/src/flash/nand/tcl.c @@ -83,7 +83,7 @@ COMMAND_HANDLER(handle_nand_info_command) struct nand_device *p; int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (NULL == p->device) { @@ -142,7 +142,7 @@ COMMAND_HANDLER(handle_nand_probe_command) struct nand_device *p; int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = nand_probe(p); @@ -161,7 +161,7 @@ COMMAND_HANDLER(handle_nand_erase_command) struct nand_device *p; int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; unsigned long offset; @@ -208,7 +208,7 @@ COMMAND_HANDLER(handle_nand_check_bad_blocks_command) struct nand_device *p; int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (CMD_ARGC == 3) { @@ -246,7 +246,7 @@ COMMAND_HANDLER(handle_nand_write_command) struct nand_fileio_state s; int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args, &s, &nand, FILEIO_READ, false, true); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; uint32_t total_bytes = s.size; @@ -261,7 +261,7 @@ COMMAND_HANDLER(handle_nand_write_command) retval = nand_write_page(nand, s.address / nand->page_size, s.page, s.page_size, s.oob, s.oob_size); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { command_print(CMD, "failed writing file %s " "to NAND flash %s at offset 0x%8.8" PRIx32, CMD_ARGV[1], CMD_ARGV[0], s.address); @@ -286,7 +286,7 @@ COMMAND_HANDLER(handle_nand_verify_command) struct nand_fileio_state file; int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args, &file, &nand, FILEIO_READ, false, true); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; struct nand_fileio_state dev; @@ -295,13 +295,13 @@ COMMAND_HANDLER(handle_nand_verify_command) dev.size = file.size; dev.oob_format = file.oob_format; retval = nand_fileio_start(CMD, nand, NULL, FILEIO_NONE, &dev); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; while (file.size > 0) { retval = nand_read_page(nand, dev.address / dev.page_size, dev.page, dev.page_size, dev.oob, dev.oob_size); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { command_print(CMD, "reading NAND flash page failed"); nand_fileio_cleanup(&dev); nand_fileio_cleanup(&file); @@ -346,14 +346,14 @@ COMMAND_HANDLER(handle_nand_dump_command) struct nand_fileio_state s; int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args, &s, &nand, FILEIO_WRITE, true, false); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; while (s.size > 0) { size_t size_written; retval = nand_read_page(nand, s.address / nand->page_size, s.page, s.page_size, s.oob, s.oob_size); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { command_print(CMD, "reading NAND flash page failed"); nand_fileio_cleanup(&s); return retval; @@ -388,7 +388,7 @@ COMMAND_HANDLER(handle_nand_raw_access_command) struct nand_device *p; int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (NULL == p->device) { @@ -530,7 +530,7 @@ static COMMAND_HELPER(create_nand_device, const char *bank_name, if (NULL != controller->commands) { retval = register_commands(CMD_CTX, NULL, controller->commands); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; } c = malloc(sizeof(struct nand_device)); @@ -552,7 +552,7 @@ static COMMAND_HELPER(create_nand_device, const char *bank_name, c->next = NULL; retval = CALL_COMMAND_HANDLER(controller->nand_device_command, c); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("'%s' driver rejected nand flash. Usage: %s", controller->name, controller->usage); diff --git a/src/flash/nor/ambiqmicro.c b/src/flash/nor/ambiqmicro.c index 162e1bb78..684d21de0 100644 --- a/src/flash/nor/ambiqmicro.c +++ b/src/flash/nor/ambiqmicro.c @@ -774,7 +774,7 @@ COMMAND_HANDLER(ambiqmicro_handle_mass_erase_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (ambiqmicro_mass_erase(bank) == ERROR_OK) { @@ -802,7 +802,7 @@ COMMAND_HANDLER(ambiqmicro_handle_page_erase_command) COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], last); retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (ambiqmicro_erase(bank, first, last) == ERROR_OK) diff --git a/src/flash/nor/atsamv.c b/src/flash/nor/atsamv.c index f70e5d010..a64c2b4cc 100644 --- a/src/flash/nor/atsamv.c +++ b/src/flash/nor/atsamv.c @@ -612,7 +612,7 @@ static int samv_get_info(struct flash_bank *bank, struct command_invocation *cmd struct samv_flash_bank *samv_info = bank->driver_priv; if (!samv_info->probed) { int r = samv_probe(bank); - if (ERROR_OK != r) + if (r != ERROR_OK) return r; } command_print_sameline(cmd, "Cortex-M7 detected with %" PRIu32 " kB flash\n", diff --git a/src/flash/nor/avrf.c b/src/flash/nor/avrf.c index b52b56b08..51f8d47f7 100644 --- a/src/flash/nor/avrf.c +++ b/src/flash/nor/avrf.c @@ -435,7 +435,7 @@ COMMAND_HANDLER(avrf_handle_mass_erase_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (avrf_mass_erase(bank) == ERROR_OK) { diff --git a/src/flash/nor/cc26xx.c b/src/flash/nor/cc26xx.c index 4d58daad8..250fc373d 100644 --- a/src/flash/nor/cc26xx.c +++ b/src/flash/nor/cc26xx.c @@ -107,9 +107,9 @@ static int cc26xx_wait_algo_done(struct flash_bank *bank, uint32_t params_addr) int retval = ERROR_OK; start_ms = timeval_ms(); - while (CC26XX_BUFFER_FULL == status) { + while (status == CC26XX_BUFFER_FULL) { retval = target_read_u32(target, status_addr, &status); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; elapsed_ms = timeval_ms() - start_ms; @@ -119,7 +119,7 @@ static int cc26xx_wait_algo_done(struct flash_bank *bank, uint32_t params_addr) break; }; - if (CC26XX_BUFFER_EMPTY != status) { + if (status != CC26XX_BUFFER_EMPTY) { LOG_ERROR("%s: Flash operation failed", cc26xx_bank->family_name); return ERROR_FAIL; } @@ -136,7 +136,7 @@ static int cc26xx_init(struct flash_bank *bank) /* Make sure we've probed the flash to get the device and size */ retval = cc26xx_auto_probe(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Check for working area to use for flash helper algorithm */ @@ -144,7 +144,7 @@ static int cc26xx_init(struct flash_bank *bank) target_free_working_area(target, cc26xx_bank->working_area); retval = target_alloc_working_area(target, cc26xx_bank->algo_working_size, &cc26xx_bank->working_area); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Confirm the defined working address is the area we need to use */ @@ -154,7 +154,7 @@ static int cc26xx_init(struct flash_bank *bank) /* Write flash helper algorithm into target memory */ retval = target_write_buffer(target, CC26XX_ALGO_BASE_ADDRESS, cc26xx_bank->algo_size, cc26xx_bank->algo_code); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("%s: Failed to load flash helper algorithm", cc26xx_bank->family_name); target_free_working_area(target, cc26xx_bank->working_area); @@ -168,7 +168,7 @@ static int cc26xx_init(struct flash_bank *bank) /* Begin executing the flash helper algorithm */ retval = target_start_algorithm(target, 0, NULL, 0, NULL, CC26XX_ALGO_BASE_ADDRESS, 0, &cc26xx_bank->armv7m_info); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("%s: Failed to start flash helper algorithm", cc26xx_bank->family_name); target_free_working_area(target, cc26xx_bank->working_area); @@ -217,7 +217,7 @@ static int cc26xx_mass_erase(struct flash_bank *bank) } retval = cc26xx_init(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Initialize algorithm parameters */ @@ -231,7 +231,7 @@ static int cc26xx_mass_erase(struct flash_bank *bank) sizeof(algo_params), (uint8_t *)&algo_params); /* Wait for command to complete */ - if (ERROR_OK == retval) + if (retval == ERROR_OK) retval = cc26xx_wait_algo_done(bank, cc26xx_bank->params_addr[0]); /* Regardless of errors, try to close down algo */ @@ -290,7 +290,7 @@ static int cc26xx_erase(struct flash_bank *bank, unsigned int first, length = (last - first + 1) * cc26xx_bank->sector_length; retval = cc26xx_init(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Set up algorithm parameters for erase command */ @@ -304,7 +304,7 @@ static int cc26xx_erase(struct flash_bank *bank, unsigned int first, sizeof(algo_params), (uint8_t *)&algo_params); /* If no error, wait for erase to finish */ - if (ERROR_OK == retval) + if (retval == ERROR_OK) retval = cc26xx_wait_algo_done(bank, cc26xx_bank->params_addr[0]); /* Regardless of errors, try to close down algo */ @@ -333,7 +333,7 @@ static int cc26xx_write(struct flash_bank *bank, const uint8_t *buffer, } retval = cc26xx_init(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Initialize algorithm parameters to default values */ @@ -354,7 +354,7 @@ static int cc26xx_write(struct flash_bank *bank, const uint8_t *buffer, /* Put next block of data to flash into buffer */ retval = target_write_buffer(target, cc26xx_bank->buffer_addr[index], size, buffer); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Unable to write data to target memory"); break; } @@ -367,13 +367,13 @@ static int cc26xx_write(struct flash_bank *bank, const uint8_t *buffer, /* Issue flash helper algorithm parameters for block write */ retval = target_write_buffer(target, cc26xx_bank->params_addr[index], sizeof(algo_params[index]), (uint8_t *)&algo_params[index]); - if (ERROR_OK != retval) + if (retval != ERROR_OK) break; /* Wait for next ping pong buffer to be ready */ index ^= 1; retval = cc26xx_wait_algo_done(bank, cc26xx_bank->params_addr[index]); - if (ERROR_OK != retval) + if (retval != ERROR_OK) break; count -= size; @@ -386,7 +386,7 @@ static int cc26xx_write(struct flash_bank *bank, const uint8_t *buffer, } /* If no error yet, wait for last buffer to finish */ - if (ERROR_OK == retval) { + if (retval == ERROR_OK) { index ^= 1; retval = cc26xx_wait_algo_done(bank, cc26xx_bank->params_addr[index]); } @@ -410,12 +410,12 @@ static int cc26xx_probe(struct flash_bank *bank) int retval; retval = target_read_u32(target, FCFG1_ICEPICK_ID, &value); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; cc26xx_bank->icepick_id = value; retval = target_read_u32(target, FCFG1_USER_ID, &value); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; cc26xx_bank->user_id = value; @@ -454,7 +454,7 @@ static int cc26xx_probe(struct flash_bank *bank) } retval = target_read_u32(target, CC26XX_FLASH_SIZE_INFO, &value); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; num_sectors = value & 0xff; if (num_sectors > max_sectors) diff --git a/src/flash/nor/cc3220sf.c b/src/flash/nor/cc3220sf.c index 1d01ba3be..88604dff4 100644 --- a/src/flash/nor/cc3220sf.c +++ b/src/flash/nor/cc3220sf.c @@ -49,12 +49,12 @@ static int cc3220sf_mass_erase(struct flash_bank *bank) /* Set starting address to erase to zero */ retval = target_write_u32(target, FMA_REGISTER_ADDR, 0); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Write the MERASE bit of the FMC register */ retval = target_write_u32(target, FMC_REGISTER_ADDR, FMC_MERASE_VALUE); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Poll the MERASE bit until the mass erase is complete */ @@ -62,7 +62,7 @@ static int cc3220sf_mass_erase(struct flash_bank *bank) start_ms = timeval_ms(); while (!done) { retval = target_read_u32(target, FMC_REGISTER_ADDR, &value); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if ((value & FMC_MERASE_BIT) == 0) { @@ -137,12 +137,12 @@ static int cc3220sf_erase(struct flash_bank *bank, unsigned int first, /* Set starting address to erase */ retval = target_write_u32(target, FMA_REGISTER_ADDR, address); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Write the ERASE bit of the FMC register */ retval = target_write_u32(target, FMC_REGISTER_ADDR, FMC_ERASE_VALUE); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Poll the ERASE bit until the erase is complete */ @@ -150,7 +150,7 @@ static int cc3220sf_erase(struct flash_bank *bank, unsigned int first, start_ms = timeval_ms(); while (!done) { retval = target_read_u32(target, FMC_REGISTER_ADDR, &value); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if ((value & FMC_ERASE_BIT) == 0) { @@ -200,13 +200,13 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, /* Obtain working area to use for flash helper algorithm */ retval = target_alloc_working_area(target, sizeof(cc3220sf_algo), &algo_working_area); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Obtain working area to use for flash buffer */ retval = target_alloc_working_area(target, target_get_working_area_avail(target), &buffer_working_area); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { target_free_working_area(target, algo_working_area); return retval; } @@ -223,7 +223,7 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, /* Write flash helper algorithm into target memory */ retval = target_write_buffer(target, algo_base_address, sizeof(cc3220sf_algo), cc3220sf_algo); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { target_free_working_area(target, algo_working_area); target_free_working_area(target, buffer_working_area); return retval; @@ -262,7 +262,7 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, /* Retrieve what is already in flash at the head address */ retval = target_read_buffer(target, head_address, sizeof(head), head); - if (ERROR_OK == retval) { + if (retval == ERROR_OK) { /* Substitute in the new data to write */ while ((remaining > 0) && (head_offset < 4)) { head[head_offset] = *buffer; @@ -273,7 +273,7 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, } } - if (ERROR_OK == retval) { + if (retval == ERROR_OK) { /* Helper parameters are passed in registers R0-R2 */ /* Set start of data buffer, address to write to, and word count */ buf_set_u32(reg_params[0].value, 0, 32, algo_buffer_address); @@ -285,12 +285,12 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, sizeof(head), head); } - if (ERROR_OK == retval) { + if (retval == ERROR_OK) { /* Execute the flash helper algorithm */ retval = target_run_algorithm(target, 0, NULL, 3, reg_params, algo_base_address, 0, FLASH_TIMEOUT, &cc3220sf_bank->armv7m_info); - if (ERROR_OK != retval) + if (retval != ERROR_OK) LOG_ERROR("cc3220sf: Flash algorithm failed to run"); /* Check that the head value was written to flash */ @@ -307,7 +307,7 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, /* Adjust remaining so it is a multiple of whole words */ remaining -= tail_count; - while ((ERROR_OK == retval) && (remaining > 0)) { + while ((retval == ERROR_OK) && (remaining > 0)) { /* Set start of data buffer and address to write to */ buf_set_u32(reg_params[0].value, 0, 32, algo_buffer_address); buf_set_u32(reg_params[1].value, 0, 32, address); @@ -317,7 +317,7 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, /* Fill up buffer with data to flash */ retval = target_write_buffer(target, algo_buffer_address, algo_buffer_size, buffer); - if (ERROR_OK != retval) + if (retval != ERROR_OK) break; /* Count to write is in 32-bit words */ @@ -331,7 +331,7 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, /* Fill buffer with what's left of the data */ retval = target_write_buffer(target, algo_buffer_address, remaining, buffer); - if (ERROR_OK != retval) + if (retval != ERROR_OK) break; /* Calculate the final word count to write */ @@ -352,7 +352,7 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, retval = target_run_algorithm(target, 0, NULL, 3, reg_params, algo_base_address, 0, FLASH_TIMEOUT, &cc3220sf_bank->armv7m_info); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("cc3220sf: Flash algorithm failed to run"); break; } @@ -369,7 +369,7 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, } /* Do one word write for any final bytes less than a full word */ - if ((ERROR_OK == retval) && (0 != tail_count)) { + if ((retval == ERROR_OK) && (0 != tail_count)) { uint8_t tail[4]; /* Set starting byte offset for data to write */ @@ -378,7 +378,7 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, /* Retrieve what is already in flash at the tail address */ retval = target_read_buffer(target, address, sizeof(tail), tail); - if (ERROR_OK == retval) { + if (retval == ERROR_OK) { /* Substitute in the new data to write */ while (tail_count > 0) { tail[tail_offset] = *buffer; @@ -388,7 +388,7 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, } } - if (ERROR_OK == retval) { + if (retval == ERROR_OK) { /* Set start of data buffer, address to write to, and word count */ buf_set_u32(reg_params[0].value, 0, 32, algo_buffer_address); buf_set_u32(reg_params[1].value, 0, 32, address); @@ -399,12 +399,12 @@ static int cc3220sf_write(struct flash_bank *bank, const uint8_t *buffer, sizeof(tail), tail); } - if (ERROR_OK == retval) { + if (retval == ERROR_OK) { /* Execute the flash helper algorithm */ retval = target_run_algorithm(target, 0, NULL, 3, reg_params, algo_base_address, 0, FLASH_TIMEOUT, &cc3220sf_bank->armv7m_info); - if (ERROR_OK != retval) + if (retval != ERROR_OK) LOG_ERROR("cc3220sf: Flash algorithm failed to run"); /* Check that the tail was written to flash */ diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c index 6461e4c72..f461956c1 100644 --- a/src/flash/nor/efm32.c +++ b/src/flash/nor/efm32.c @@ -232,7 +232,7 @@ static int efm32x_read_info(struct flash_bank *bank, memset(efm32_info, 0, sizeof(struct efm32_info)); ret = target_read_u32(bank->target, CPUID, &cpuid); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ret; if (((cpuid >> 4) & 0xfff) == 0xc23) { @@ -247,23 +247,23 @@ static int efm32x_read_info(struct flash_bank *bank, } ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib)); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ret; ret = efm32x_get_ram_size(bank, &(efm32_info->ram_sz_kib)); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ret; ret = efm32x_get_part_num(bank, &(efm32_info->part_num)); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ret; ret = efm32x_get_part_family(bank, &(efm32_info->part_family)); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ret; ret = efm32x_get_prod_rev(bank, &(efm32_info->prod_rev)); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ret; for (size_t i = 0; i < ARRAY_SIZE(efm32_families); i++) { @@ -296,7 +296,7 @@ static int efm32x_read_info(struct flash_bank *bank, uint8_t pg_size = 0; ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE, &pg_size); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ret; efm32_info->page_size = (1 << ((pg_size+10) & 0xff)); @@ -349,7 +349,7 @@ static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg, uint32_t reg_val = 0; ret = efm32x_read_reg_u32(bank, reg, ®_val); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ret; if (set) @@ -381,7 +381,7 @@ static int efm32x_wait_status(struct flash_bank *bank, int timeout, while (1) { ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status); - if (ERROR_OK != ret) + if (ret != ERROR_OK) break; LOG_DEBUG("status: 0x%" PRIx32 "", status); @@ -420,16 +420,16 @@ static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr) LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr); ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ret; ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD, EFM32_MSC_WRITECMD_LADDRIM_MASK, 1); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ret; ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ret; LOG_DEBUG("status 0x%" PRIx32, status); @@ -444,7 +444,7 @@ static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr) ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD, EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ret; return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO, @@ -464,14 +464,14 @@ static int efm32x_erase(struct flash_bank *bank, unsigned int first, efm32x_msc_lock(bank, 0); ret = efm32x_set_wren(bank, 1); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("Failed to enable MSC write"); return ret; } for (unsigned int i = first; i <= last; i++) { ret = efm32x_erase_page(bank, bank->sectors[i].offset); - if (ERROR_OK != ret) + if (ret != ERROR_OK) LOG_ERROR("Failed to erase page %d", i); } @@ -498,7 +498,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank) for (int i = 0; i < data_size; i++, ptr++) { ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("Failed to read PLW %d", i); return ret; } @@ -509,7 +509,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank) /* ULW, word 126 */ ptr = efm32x_info->lb_page + 126; ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("Failed to read ULW"); return ret; } @@ -517,7 +517,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank) /* DLW, word 127 */ ptr = efm32x_info->lb_page + 127; ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("Failed to read DLW"); return ret; } @@ -525,7 +525,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank) /* MLW, word 125, present in GG, LG, PG, JG, EFR32 */ ptr = efm32x_info->lb_page + 125; ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("Failed to read MLW"); return ret; } @@ -533,7 +533,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank) /* ALW, word 124, present in GG, LG, PG, JG, EFR32 */ ptr = efm32x_info->lb_page + 124; ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+124*4, ptr); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("Failed to read ALW"); return ret; } @@ -541,7 +541,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank) /* CLW1, word 123, present in EFR32 */ ptr = efm32x_info->lb_page + 123; ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+123*4, ptr); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("Failed to read CLW1"); return ret; } @@ -549,7 +549,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank) /* CLW0, word 122, present in GG, LG, PG, JG, EFR32 */ ptr = efm32x_info->lb_page + 122; ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+122*4, ptr); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("Failed to read CLW0"); return ret; } @@ -563,7 +563,7 @@ static int efm32x_write_lock_data(struct flash_bank *bank) int ret = 0; ret = efm32x_erase_page(bank, EFM32_MSC_LOCK_BITS); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("Failed to erase LB page"); return ret; } @@ -617,14 +617,14 @@ static int efm32x_protect(struct flash_bank *bank, int set, unsigned int first, for (unsigned int i = first; i <= last; i++) { ret = efm32x_set_page_lock(bank, i, set); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("Failed to set lock on page %d", i); return ret; } } ret = efm32x_write_lock_data(bank); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("Failed to write LB page"); return ret; } @@ -812,16 +812,16 @@ static int efm32x_write_word(struct flash_bank *bank, uint32_t addr, keep_alive(); ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ret; ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD, EFM32_MSC_WRITECMD_LADDRIM_MASK, 1); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ret; ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ret; LOG_DEBUG("status 0x%" PRIx32, status); @@ -836,27 +836,27 @@ static int efm32x_write_word(struct flash_bank *bank, uint32_t addr, ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO, EFM32_MSC_STATUS_WDATAREADY_MASK, 1); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("Wait for WDATAREADY failed"); return ret; } ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WDATA, val); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("WDATA write failed"); return ret; } ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WRITECMD, EFM32_MSC_WRITECMD_WRITEONCE_MASK); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("WRITECMD write failed"); return ret; } ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO, EFM32_MSC_STATUS_BUSY_MASK, 0); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("Wait for BUSY failed"); return ret; } @@ -950,7 +950,7 @@ static int efm32x_probe(struct flash_bank *bank) memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ); ret = efm32x_read_info(bank, &efm32_mcu_info); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ret; LOG_INFO("detected part: %s Gecko, rev %d", @@ -973,7 +973,7 @@ static int efm32x_probe(struct flash_bank *bank) bank->num_sectors = num_pages; ret = efm32x_read_lock_data(bank); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("Failed to read LB data"); return ret; } @@ -1011,7 +1011,7 @@ static int efm32x_protect_check(struct flash_bank *bank) } ret = efm32x_read_lock_data(bank); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("Failed to read LB data"); return ret; } @@ -1030,7 +1030,7 @@ static int get_efm32x_info(struct flash_bank *bank, struct command_invocation *c int ret; ret = efm32x_read_info(bank, &info); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { LOG_ERROR("Failed to read EFM32 info"); return ret; } @@ -1048,7 +1048,7 @@ COMMAND_HANDLER(efm32x_handle_debuglock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; struct efm32x_flash_bank *efm32x_info = bank->driver_priv; @@ -1065,7 +1065,7 @@ COMMAND_HANDLER(efm32x_handle_debuglock_command) *ptr = 0; retval = efm32x_write_lock_data(bank); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Failed to write LB page"); return retval; } diff --git a/src/flash/nor/em357.c b/src/flash/nor/em357.c index 4e2a169c6..2597d8beb 100644 --- a/src/flash/nor/em357.c +++ b/src/flash/nor/em357.c @@ -761,7 +761,7 @@ COMMAND_HANDLER(em357_handle_lock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; em357_info = bank->driver_priv; @@ -800,7 +800,7 @@ COMMAND_HANDLER(em357_handle_unlock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; target = bank->target; @@ -873,7 +873,7 @@ COMMAND_HANDLER(em357_handle_mass_erase_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = em357_mass_erase(bank); diff --git a/src/flash/nor/fm3.c b/src/flash/nor/fm3.c index c5eab5124..dc7dd40be 100644 --- a/src/flash/nor/fm3.c +++ b/src/flash/nor/fm3.c @@ -949,7 +949,7 @@ COMMAND_HANDLER(fm3_handle_chip_erase_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (fm3_chip_erase(bank) == ERROR_OK) { diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c index 754957e54..465199d79 100644 --- a/src/flash/nor/lpc2000.c +++ b/src/flash/nor/lpc2000.c @@ -1569,7 +1569,7 @@ COMMAND_HANDLER(lpc2000_handle_part_id_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (bank->target->state != TARGET_HALTED) { diff --git a/src/flash/nor/lpc2900.c b/src/flash/nor/lpc2900.c index 4d3d7f758..4bf52974b 100644 --- a/src/flash/nor/lpc2900.c +++ b/src/flash/nor/lpc2900.c @@ -487,7 +487,7 @@ COMMAND_HANDLER(lpc2900_handle_signature_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (bank->target->state != TARGET_HALTED) { @@ -522,7 +522,7 @@ COMMAND_HANDLER(lpc2900_handle_read_custom_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; struct lpc2900_flash_bank *lpc2900_info = bank->driver_priv; @@ -584,7 +584,7 @@ COMMAND_HANDLER(lpc2900_handle_password_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; struct lpc2900_flash_bank *lpc2900_info = bank->driver_priv; @@ -614,7 +614,7 @@ COMMAND_HANDLER(lpc2900_handle_write_custom_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; struct lpc2900_flash_bank *lpc2900_info = bank->driver_priv; @@ -713,7 +713,7 @@ COMMAND_HANDLER(lpc2900_handle_secure_sector_command) /* Get the bank descriptor */ struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; struct lpc2900_flash_bank *lpc2900_info = bank->driver_priv; @@ -794,7 +794,7 @@ COMMAND_HANDLER(lpc2900_handle_secure_jtag_command) /* Get the bank descriptor */ struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; struct lpc2900_flash_bank *lpc2900_info = bank->driver_priv; diff --git a/src/flash/nor/max32xxx.c b/src/flash/nor/max32xxx.c index 33d786889..a1bb668eb 100644 --- a/src/flash/nor/max32xxx.c +++ b/src/flash/nor/max32xxx.c @@ -768,7 +768,7 @@ COMMAND_HANDLER(max32xxx_handle_mass_erase_command) return ERROR_OK; } - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (max32xxx_mass_erase(bank) == ERROR_OK) { @@ -796,7 +796,7 @@ COMMAND_HANDLER(max32xxx_handle_protection_set_command) } retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; info = bank->driver_priv; @@ -852,7 +852,7 @@ COMMAND_HANDLER(max32xxx_handle_protection_clr_command) } retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; info = bank->driver_priv; @@ -907,13 +907,13 @@ COMMAND_HANDLER(max32xxx_handle_protection_check_command) } retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; info = bank->driver_priv; /* Update the protection array */ retval = max32xxx_protect_check(bank); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_WARNING("Error updating the protection array"); return retval; } diff --git a/src/flash/nor/msp432.c b/src/flash/nor/msp432.c index 22f7c77a2..b418bf152 100644 --- a/src/flash/nor/msp432.c +++ b/src/flash/nor/msp432.c @@ -63,7 +63,7 @@ static int msp432_device_type(uint32_t family_type, uint32_t device_id, { int device_type = MSP432_NO_TYPE; - if (MSP432E4 == family_type) { + if (family_type == MSP432E4) { /* MSP432E4 device family */ if (device_id == 0x180C0002) { @@ -191,7 +191,7 @@ static int msp432_exec_cmd(struct target *target, struct msp432_algo_params /* Write out parameters to target memory */ retval = target_write_buffer(target, ALGO_PARAMS_BASE_ADDR, sizeof(struct msp432_algo_params), (uint8_t *)algo_params); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Write out command to target memory */ @@ -209,9 +209,9 @@ static int msp432_wait_return_code(struct target *target) int retval = ERROR_OK; start_ms = timeval_ms(); - while ((0 == return_code) || (FLASH_BUSY == return_code)) { + while ((0 == return_code) || (return_code == FLASH_BUSY)) { retval = target_read_u32(target, ALGO_RETURN_CODE_ADDR, &return_code); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; elapsed_ms = timeval_ms() - start_ms; @@ -221,7 +221,7 @@ static int msp432_wait_return_code(struct target *target) break; }; - if (FLASH_SUCCESS != return_code) { + if (return_code != FLASH_SUCCESS) { LOG_ERROR("msp432: Flash operation failed: %s", msp432_return_text(return_code)); return ERROR_FAIL; @@ -251,9 +251,9 @@ static int msp432_wait_inactive(struct target *target, uint32_t buffer) } start_ms = timeval_ms(); - while (BUFFER_INACTIVE != status_code) { + while (status_code != BUFFER_INACTIVE) { retval = target_read_u32(target, status_addr, &status_code); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; elapsed_ms = timeval_ms() - start_ms; @@ -263,7 +263,7 @@ static int msp432_wait_inactive(struct target *target, uint32_t buffer) break; }; - if (BUFFER_INACTIVE != status_code) { + if (status_code != BUFFER_INACTIVE) { LOG_ERROR( "msp432: Flash operation failed: buffer not written to flash"); return ERROR_FAIL; @@ -286,7 +286,7 @@ static int msp432_init(struct flash_bank *bank) /* Make sure we've probed the flash to get the device and size */ retval = msp432_auto_probe(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Choose appropriate flash helper algorithm */ @@ -339,7 +339,7 @@ static int msp432_init(struct flash_bank *bank) target_free_working_area(target, msp432_bank->working_area); retval = target_alloc_working_area(target, ALGO_WORKING_SIZE, &msp432_bank->working_area); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Confirm the defined working address is the area we need to use */ @@ -349,7 +349,7 @@ static int msp432_init(struct flash_bank *bank) /* Write flash helper algorithm into target memory */ retval = target_write_buffer(target, ALGO_BASE_ADDR, loader_size, loader_code); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Initialize the ARMv7 specific info to run the algorithm */ @@ -362,7 +362,7 @@ static int msp432_init(struct flash_bank *bank) /* Write out parameters to target memory */ retval = target_write_buffer(target, ALGO_PARAMS_BASE_ADDR, sizeof(algo_params), (uint8_t *)&algo_params); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Initialize stack pointer for flash helper algorithm */ @@ -373,7 +373,7 @@ static int msp432_init(struct flash_bank *bank) retval = target_start_algorithm(target, 0, 0, 1, reg_params, algo_entry_addr, 0, &msp432_bank->armv7m_info); destroy_reg_param(®_params[0]); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("msp432: Failed to start flash helper algorithm"); return retval; } @@ -385,7 +385,7 @@ static int msp432_init(struct flash_bank *bank) /* Issue the init command to the flash helper algorithm */ retval = msp432_exec_cmd(target, &algo_params, FLASH_INIT); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = msp432_wait_return_code(target); @@ -406,7 +406,7 @@ static int msp432_quit(struct flash_bank *bank) /* Issue the exit command to the flash helper algorithm */ retval = msp432_exec_cmd(target, &algo_params, FLASH_EXIT); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; (void)msp432_wait_return_code(target); @@ -438,7 +438,7 @@ static int msp432_mass_erase(struct flash_bank *bank, bool all) } retval = msp432_init(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Initialize algorithm parameters to default values */ @@ -452,19 +452,19 @@ static int msp432_mass_erase(struct flash_bank *bank, bool all) /* Issue the mass erase command to the flash helper algorithm */ retval = msp432_exec_cmd(target, &algo_params, FLASH_MASS_ERASE); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { (void)msp432_quit(bank); return retval; } retval = msp432_wait_return_code(target); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { (void)msp432_quit(bank); return retval; } retval = msp432_quit(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; return retval; @@ -507,7 +507,7 @@ COMMAND_HANDLER(msp432_mass_erase_command) } retval = msp432_mass_erase(bank, all); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (MSP432E4 == msp432_bank->family_type) { @@ -614,7 +614,7 @@ static int msp432_erase(struct flash_bank *bank, unsigned int first, } retval = msp432_init(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Initialize algorithm parameters to default values */ @@ -646,20 +646,20 @@ static int msp432_erase(struct flash_bank *bank, unsigned int first, /* Issue the sector erase command to the flash helper algorithm */ retval = msp432_exec_cmd(target, &algo_params, FLASH_SECTOR_ERASE); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { (void)msp432_quit(bank); return retval; } retval = msp432_wait_return_code(target); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { (void)msp432_quit(bank); return retval; } } retval = msp432_quit(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; return retval; @@ -705,7 +705,7 @@ static int msp432_write(struct flash_bank *bank, const uint8_t *buffer, if (offset < start) { uint32_t start_count = MIN(start - offset, count); retval = msp432_write(bank, buffer, offset, start_count); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; } /* Send a request for anything after read-only sectors */ @@ -723,7 +723,7 @@ static int msp432_write(struct flash_bank *bank, const uint8_t *buffer, } retval = msp432_init(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Initialize algorithm parameters to default values */ @@ -742,7 +742,7 @@ static int msp432_write(struct flash_bank *bank, const uint8_t *buffer, /* Set up flash helper algorithm to continuous flash mode */ retval = msp432_exec_cmd(target, &algo_params, FLASH_CONTINUOUS); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { (void)msp432_quit(bank); return retval; } @@ -758,7 +758,7 @@ static int msp432_write(struct flash_bank *bank, const uint8_t *buffer, /* Put next block of data to flash into buffer */ retval = target_write_buffer(target, ALGO_BUFFER1_ADDR, size, buffer); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Unable to write data to target memory"); (void)msp432_quit(bank); return ERROR_FLASH_OPERATION_FAILED; @@ -767,13 +767,13 @@ static int msp432_write(struct flash_bank *bank, const uint8_t *buffer, /* Signal the flash helper algorithm that data is ready to flash */ retval = target_write_u32(target, ALGO_BUFFER1_STATUS_ADDR, data_ready); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { (void)msp432_quit(bank); return ERROR_FLASH_OPERATION_FAILED; } retval = msp432_wait_inactive(target, 1); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { (void)msp432_quit(bank); return retval; } @@ -788,13 +788,13 @@ static int msp432_write(struct flash_bank *bank, const uint8_t *buffer, /* Confirm that the flash helper algorithm is finished */ retval = msp432_wait_return_code(target); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { (void)msp432_quit(bank); return retval; } retval = msp432_quit(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; return retval; @@ -826,7 +826,7 @@ static int msp432_probe(struct flash_bank *bank) /* Read the flash size register to determine this is a P4 or not */ /* MSP432P4s will return the size of flash. MSP432E4s will return zero */ retval = target_read_u32(target, P4_FLASH_MAIN_SIZE_REG, &size); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (0 == size) { @@ -834,13 +834,13 @@ static int msp432_probe(struct flash_bank *bank) msp432_bank->family_type = MSP432E4; retval = target_read_u32(target, E4_DID0_REG, &device_id); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; msp432_bank->device_id = device_id; retval = target_read_u32(target, E4_DID1_REG, &hardware_rev); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; msp432_bank->hardware_rev = hardware_rev; @@ -849,13 +849,13 @@ static int msp432_probe(struct flash_bank *bank) msp432_bank->family_type = MSP432P4; retval = target_read_u32(target, P4_DEVICE_ID_REG, &device_id); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; msp432_bank->device_id = device_id & 0xFFFF; retval = target_read_u32(target, P4_HARDWARE_REV_REG, &hardware_rev); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; msp432_bank->hardware_rev = hardware_rev & 0xFF; @@ -868,7 +868,7 @@ static int msp432_probe(struct flash_bank *bank) /* Set up MSP432P4 specific flash parameters */ if (is_main) { retval = target_read_u32(target, P4_FLASH_MAIN_SIZE_REG, &size); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; sector_length = P4_SECTOR_LENGTH; @@ -878,7 +878,7 @@ static int msp432_probe(struct flash_bank *bank) msp432_bank->device_type == MSP432P411X_GUESS) { /* MSP432P411x has an info size register, use that for size */ retval = target_read_u32(target, P4_FLASH_INFO_SIZE_REG, &size); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; } else { /* All other MSP432P401x devices have fixed info region size */ diff --git a/src/flash/nor/pic32mx.c b/src/flash/nor/pic32mx.c index dc6b28d82..38f900f3e 100644 --- a/src/flash/nor/pic32mx.c +++ b/src/flash/nor/pic32mx.c @@ -848,7 +848,7 @@ COMMAND_HANDLER(pic32mx_handle_pgm_word_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 2, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (address < bank->base || address >= (bank->base + bank->size)) { @@ -885,7 +885,7 @@ COMMAND_HANDLER(pic32mx_handle_unlock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; target = bank->target; diff --git a/src/flash/nor/psoc4.c b/src/flash/nor/psoc4.c index cc2521b0d..28c212422 100644 --- a/src/flash/nor/psoc4.c +++ b/src/flash/nor/psoc4.c @@ -624,7 +624,7 @@ COMMAND_HANDLER(psoc4_handle_flash_autoerase_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; struct psoc4_flash_bank *psoc4_info = bank->driver_priv; @@ -898,7 +898,7 @@ COMMAND_HANDLER(psoc4_handle_mass_erase_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = psoc4_mass_erase(bank); diff --git a/src/flash/nor/sim3x.c b/src/flash/nor/sim3x.c index b42add96e..a84fcf0e3 100644 --- a/src/flash/nor/sim3x.c +++ b/src/flash/nor/sim3x.c @@ -1039,7 +1039,7 @@ COMMAND_HANDLER(sim3x_lock) return retval; ret = sim3x_flash_write(bank, lock_word, LOCK_WORD_ADDRESS, 4); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ret; LOG_INFO("Target is successfully locked"); diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c index 1e1ff6007..569c09b46 100644 --- a/src/flash/nor/stellaris.c +++ b/src/flash/nor/stellaris.c @@ -1315,7 +1315,7 @@ COMMAND_HANDLER(stellaris_handle_mass_erase_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (stellaris_mass_erase(bank) == ERROR_OK) { diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c index fbcf83afb..d50e0d80e 100644 --- a/src/flash/nor/stm32f1x.c +++ b/src/flash/nor/stm32f1x.c @@ -349,7 +349,7 @@ static int stm32x_protect_check(struct flash_bank *bank) uint32_t protection; int retval = stm32x_check_operation_supported(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* medium density - each bit refers to a 4 sector protection block @@ -1197,7 +1197,7 @@ COMMAND_HANDLER(stm32x_handle_lock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; stm32x_info = bank->driver_priv; @@ -1210,7 +1210,7 @@ COMMAND_HANDLER(stm32x_handle_lock_command) } retval = stm32x_check_operation_supported(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (stm32x_erase_options(bank) != ERROR_OK) { @@ -1240,7 +1240,7 @@ COMMAND_HANDLER(stm32x_handle_unlock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; target = bank->target; @@ -1251,7 +1251,7 @@ COMMAND_HANDLER(stm32x_handle_unlock_command) } retval = stm32x_check_operation_supported(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (stm32x_erase_options(bank) != ERROR_OK) { @@ -1282,7 +1282,7 @@ COMMAND_HANDLER(stm32x_handle_options_read_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; stm32x_info = bank->driver_priv; @@ -1295,7 +1295,7 @@ COMMAND_HANDLER(stm32x_handle_options_read_command) } retval = stm32x_check_operation_supported(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte); @@ -1349,7 +1349,7 @@ COMMAND_HANDLER(stm32x_handle_options_write_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; stm32x_info = bank->driver_priv; @@ -1362,11 +1362,11 @@ COMMAND_HANDLER(stm32x_handle_options_write_command) } retval = stm32x_check_operation_supported(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32x_read_options(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* start with current options */ @@ -1438,7 +1438,7 @@ COMMAND_HANDLER(stm32x_handle_options_load_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; struct stm32x_flash_bank *stm32x_info = bank->driver_priv; @@ -1457,7 +1457,7 @@ COMMAND_HANDLER(stm32x_handle_options_load_command) } retval = stm32x_check_operation_supported(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* unlock option flash registers */ @@ -1520,7 +1520,7 @@ COMMAND_HANDLER(stm32x_handle_mass_erase_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32x_mass_erase(bank); diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c index f718e3b98..00e6be0ac 100644 --- a/src/flash/nor/stm32f2x.c +++ b/src/flash/nor/stm32f2x.c @@ -1430,7 +1430,7 @@ COMMAND_HANDLER(stm32x_handle_lock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; stm32x_info = bank->driver_priv; @@ -1469,7 +1469,7 @@ COMMAND_HANDLER(stm32x_handle_unlock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; stm32x_info = bank->driver_priv; @@ -1556,7 +1556,7 @@ COMMAND_HANDLER(stm32x_handle_mass_erase_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32x_mass_erase(bank); @@ -1585,11 +1585,11 @@ COMMAND_HANDLER(stm32f2x_handle_options_read_command) } retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32x_read_options(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; stm32x_info = bank->driver_priv; @@ -1631,11 +1631,11 @@ COMMAND_HANDLER(stm32f2x_handle_options_write_command) } retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32x_read_options(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; stm32x_info = bank->driver_priv; @@ -1693,7 +1693,7 @@ COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command) } retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; stm32x_info = bank->driver_priv; @@ -1707,7 +1707,7 @@ COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command) " finally unlock it. Clears PCROP and mass erases flash."); retval = stm32x_read_options(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], optcr2_pcrop); @@ -1731,7 +1731,7 @@ COMMAND_HANDLER(stm32x_handle_otp_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (stm32x_is_otp(bank)) { if (strcmp(CMD_ARGV[1], "enable") == 0) { diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c index 4c503db38..16ab6aeb7 100644 --- a/src/flash/nor/stm32h7x.c +++ b/src/flash/nor/stm32h7x.c @@ -1003,7 +1003,7 @@ COMMAND_HANDLER(stm32x_handle_lock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32x_set_rdp(bank, OPT_RDP_L1); @@ -1023,7 +1023,7 @@ COMMAND_HANDLER(stm32x_handle_unlock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32x_set_rdp(bank, OPT_RDP_L0); @@ -1083,7 +1083,7 @@ COMMAND_HANDLER(stm32x_handle_mass_erase_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32x_mass_erase(bank); @@ -1109,14 +1109,14 @@ COMMAND_HANDLER(stm32x_handle_option_read_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; uint32_t reg_offset, value; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset); retval = stm32x_read_flash_reg(bank, reg_offset, &value); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32, @@ -1134,7 +1134,7 @@ COMMAND_HANDLER(stm32x_handle_option_write_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; uint32_t reg_offset, value, mask = 0xffffffff; diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c index aa4171e0c..9e460a251 100644 --- a/src/flash/nor/stm32l4x.c +++ b/src/flash/nor/stm32l4x.c @@ -1708,7 +1708,7 @@ COMMAND_HANDLER(stm32l4_handle_mass_erase_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32l4_mass_erase(bank); @@ -1734,7 +1734,7 @@ COMMAND_HANDLER(stm32l4_handle_option_read_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; uint32_t reg_offset, reg_addr; @@ -1744,7 +1744,7 @@ COMMAND_HANDLER(stm32l4_handle_option_read_command) reg_addr = stm32l4_get_flash_reg(bank, reg_offset); retval = stm32l4_read_flash_reg(bank, reg_offset, &value); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value); @@ -1761,7 +1761,7 @@ COMMAND_HANDLER(stm32l4_handle_option_write_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; uint32_t reg_offset; @@ -1788,15 +1788,15 @@ COMMAND_HANDLER(stm32l4_handle_option_load_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32l4_unlock_reg(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32l4_unlock_option_reg(bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload, @@ -1824,7 +1824,7 @@ COMMAND_HANDLER(stm32l4_handle_lock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (stm32l4_is_otp(bank)) { @@ -1859,7 +1859,7 @@ COMMAND_HANDLER(stm32l4_handle_unlock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (stm32l4_is_otp(bank)) { @@ -1891,7 +1891,7 @@ COMMAND_HANDLER(stm32l4_handle_wrp_info_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (stm32l4_is_otp(bank)) { @@ -1963,7 +1963,7 @@ COMMAND_HANDLER(stm32l4_handle_otp_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (!stm32l4_is_otp(bank)) { diff --git a/src/flash/nor/stm32lx.c b/src/flash/nor/stm32lx.c index 5ca424b87..e8655aa80 100644 --- a/src/flash/nor/stm32lx.c +++ b/src/flash/nor/stm32lx.c @@ -313,7 +313,7 @@ COMMAND_HANDLER(stm32lx_handle_mass_erase_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32lx_mass_erase(bank); @@ -337,7 +337,7 @@ COMMAND_HANDLER(stm32lx_handle_lock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32lx_lock(bank); @@ -357,7 +357,7 @@ COMMAND_HANDLER(stm32lx_handle_unlock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = stm32lx_unlock(bank); diff --git a/src/flash/nor/stmqspi.c b/src/flash/nor/stmqspi.c index 978188ec1..e8e006130 100644 --- a/src/flash/nor/stmqspi.c +++ b/src/flash/nor/stmqspi.c @@ -509,7 +509,7 @@ COMMAND_HANDLER(stmqspi_handle_mass_erase_command) return ERROR_COMMAND_SYNTAX_ERROR; retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; stmqspi_info = bank->driver_priv; @@ -638,7 +638,7 @@ COMMAND_HANDLER(stmqspi_handle_set) return ERROR_COMMAND_SYNTAX_ERROR; retval = CALL_COMMAND_HANDLER(flash_command_get_bank, index++, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; target = bank->target; @@ -808,7 +808,7 @@ COMMAND_HANDLER(stmqspi_handle_cmd) } retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; target = bank->target; diff --git a/src/flash/nor/str7x.c b/src/flash/nor/str7x.c index cce871081..5f3ff0069 100644 --- a/src/flash/nor/str7x.c +++ b/src/flash/nor/str7x.c @@ -728,7 +728,7 @@ COMMAND_HANDLER(str7x_handle_disable_jtag_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; str7x_info = bank->driver_priv; diff --git a/src/flash/nor/str9x.c b/src/flash/nor/str9x.c index 87ffec877..5c3a9cb2b 100644 --- a/src/flash/nor/str9x.c +++ b/src/flash/nor/str9x.c @@ -611,7 +611,7 @@ COMMAND_HANDLER(str9x_handle_flash_config_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; uint32_t bbsr, nbbsr, bbadr, nbbadr; diff --git a/src/flash/nor/str9xpec.c b/src/flash/nor/str9xpec.c index 9946b06fb..1d9e59e82 100644 --- a/src/flash/nor/str9xpec.c +++ b/src/flash/nor/str9xpec.c @@ -727,7 +727,7 @@ COMMAND_HANDLER(str9xpec_handle_part_id_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; str9xpec_info = bank->driver_priv; @@ -768,7 +768,7 @@ COMMAND_HANDLER(str9xpec_handle_flash_options_read_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; str9xpec_info = bank->driver_priv; @@ -877,7 +877,7 @@ COMMAND_HANDLER(str9xpec_handle_flash_options_write_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; status = str9xpec_write_options(bank); @@ -901,7 +901,7 @@ COMMAND_HANDLER(str9xpec_handle_flash_options_cmap_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; str9xpec_info = bank->driver_priv; @@ -923,7 +923,7 @@ COMMAND_HANDLER(str9xpec_handle_flash_options_lvdthd_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; str9xpec_info = bank->driver_priv; @@ -945,7 +945,7 @@ COMMAND_HANDLER(str9xpec_handle_flash_options_lvdsel_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; str9xpec_info = bank->driver_priv; @@ -967,7 +967,7 @@ COMMAND_HANDLER(str9xpec_handle_flash_options_lvdwarn_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; str9xpec_info = bank->driver_priv; @@ -989,7 +989,7 @@ COMMAND_HANDLER(str9xpec_handle_flash_lock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; status = str9xpec_lock_device(bank); @@ -1009,7 +1009,7 @@ COMMAND_HANDLER(str9xpec_handle_flash_unlock_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; status = str9xpec_unlock_device(bank); @@ -1036,7 +1036,7 @@ COMMAND_HANDLER(str9xpec_handle_flash_enable_turbo_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; str9xpec_info = bank->driver_priv; @@ -1083,7 +1083,7 @@ COMMAND_HANDLER(str9xpec_handle_flash_disable_turbo_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; str9xpec_info = bank->driver_priv; diff --git a/src/flash/nor/swm050.c b/src/flash/nor/swm050.c index 98361eb91..be7452b81 100644 --- a/src/flash/nor/swm050.c +++ b/src/flash/nor/swm050.c @@ -142,7 +142,7 @@ COMMAND_HANDLER(swm050_handle_mass_erase_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = swm050_mass_erase(bank); diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c index 199bf2d4e..1705384c7 100644 --- a/src/flash/nor/tcl.c +++ b/src/flash/nor/tcl.c @@ -195,7 +195,7 @@ COMMAND_HANDLER(handle_flash_erase_check_command) struct flash_bank *p; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = p->driver->erase_check(p); @@ -286,7 +286,7 @@ COMMAND_HANDLER(handle_flash_erase_address_command) if (retval == ERROR_OK) retval = flash_erase_address_range(target, do_pad, address, length); - if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) { + if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) { command_print(CMD, "erased address " TARGET_ADDR_FMT " (length %" PRIu32 ")" " in %fs (%0.3f KiB/s)", address, length, duration_elapsed(&bench), duration_kbps(&bench, length)); @@ -334,7 +334,7 @@ COMMAND_HANDLER(handle_flash_erase_command) retval = flash_driver_erase(p, first, last); - if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) { + if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) { command_print(CMD, "erased sectors %" PRIu32 " " "through %" PRIu32 " on flash bank %u " "in %fs", first, last, p->bank_number, duration_elapsed(&bench)); @@ -460,7 +460,7 @@ COMMAND_HANDLER(handle_flash_write_image_command) return retval; } - if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) { + if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) { command_print(CMD, "wrote %" PRIu32 " bytes from file %s " "in %fs (%0.3f KiB/s)", written, CMD_ARGV[0], duration_elapsed(&bench), duration_kbps(&bench, written)); @@ -512,7 +512,7 @@ COMMAND_HANDLER(handle_flash_verify_image_command) return retval; } - if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) { + if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) { command_print(CMD, "verified %" PRIu32 " bytes from file %s " "in %fs (%0.3f KiB/s)", verified, CMD_ARGV[0], duration_elapsed(&bench), duration_kbps(&bench, verified)); @@ -754,7 +754,7 @@ COMMAND_HANDLER(handle_flash_write_bank_command) struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; offset = 0; @@ -841,7 +841,7 @@ COMMAND_HANDLER(handle_flash_write_bank_command) free(buffer); - if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) { + if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) { command_print(CMD, "wrote %zu bytes from file %s to flash bank %u" " at offset 0x%8.8" PRIx32 " in %fs (%0.3f KiB/s)", length, CMD_ARGV[1], bank->bank_number, offset, @@ -870,7 +870,7 @@ COMMAND_HANDLER(handle_flash_read_bank_command) struct flash_bank *p; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; offset = 0; @@ -951,7 +951,7 @@ COMMAND_HANDLER(handle_flash_verify_bank_command) struct flash_bank *p; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; offset = 0; @@ -1072,7 +1072,7 @@ COMMAND_HANDLER(handle_flash_padded_value_command) struct flash_bank *p; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &p); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], p->default_padded_value); @@ -1286,7 +1286,7 @@ COMMAND_HANDLER(handle_flash_bank_command) if (NULL != driver->commands) { int retval = register_commands(CMD_CTX, NULL, driver->commands); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("couldn't register '%s' commands", driver_name); return ERROR_FAIL; @@ -1306,7 +1306,7 @@ COMMAND_HANDLER(handle_flash_bank_command) int retval; retval = CALL_COMMAND_HANDLER(driver->flash_bank_command, c); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("'%s' driver rejected flash bank at " TARGET_ADDR_FMT "; usage: %s", driver_name, c->base, driver->usage); free(c); diff --git a/src/flash/nor/xcf.c b/src/flash/nor/xcf.c index 1220a1ef2..1a37e9c5b 100644 --- a/src/flash/nor/xcf.c +++ b/src/flash/nor/xcf.c @@ -475,7 +475,7 @@ static int read_write_data(struct flash_bank *bank, const uint8_t *w_buffer, w_buffer += len; sector_bytes -= len; ret = isc_program_data_page(bank, page_buf); - if (ERROR_OK != ret) + if (ret != ERROR_OK) goto EXIT; else { LOG_DEBUG("written %d bytes from %d", dbg_written, dbg_count); @@ -494,7 +494,7 @@ static int read_write_data(struct flash_bank *bank, const uint8_t *w_buffer, if (write_flag) { for (unsigned int i = 0; i < bank->num_sectors; i++) { ret = isc_set_data_done(bank, i); - if (ERROR_OK != ret) + if (ret != ERROR_OK) goto EXIT; } } @@ -755,7 +755,7 @@ COMMAND_HANDLER(xcf_handle_ccb_command) { struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; uint16_t ccb = 0xFFFF; @@ -800,29 +800,29 @@ COMMAND_HANDLER(xcf_handle_ccb_command) { sector = gucr_num(bank); isc_clear_protect(bank, sector, sector); int ret = isc_erase_sectors(bank, sector, sector); - if (ERROR_OK != ret) + if (ret != ERROR_OK) goto EXIT; ret = isc_program_ccb(bank, ccb); - if (ERROR_OK != ret) + if (ret != ERROR_OK) goto EXIT; ret = isc_program_single_revision_btc(bank); - if (ERROR_OK != ret) + if (ret != ERROR_OK) goto EXIT; ret = isc_set_data_done(bank, sector); - if (ERROR_OK != ret) + if (ret != ERROR_OK) goto EXIT; /* SUCR sector */ sector = sucr_num(bank); isc_clear_protect(bank, sector, sector); ret = isc_erase_sectors(bank, sector, sector); - if (ERROR_OK != ret) + if (ret != ERROR_OK) goto EXIT; ret = isc_program_singe_revision_sucr(bank); - if (ERROR_OK != ret) + if (ret != ERROR_OK) goto EXIT; ret = isc_set_data_done(bank, sector); - if (ERROR_OK != ret) + if (ret != ERROR_OK) goto EXIT; EXIT: @@ -838,7 +838,7 @@ COMMAND_HANDLER(xcf_handle_configure_command) { struct flash_bank *bank; int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; return fpga_configure(bank); diff --git a/src/hello.c b/src/hello.c index a1c00c0dd..9d078c0e7 100644 --- a/src/hello.c +++ b/src/hello.c @@ -88,7 +88,7 @@ COMMAND_HANDLER(handle_hello_command) { const char *sep, *name; int retval = CALL_COMMAND_HANDLER(handle_hello_args, &sep, &name); - if (ERROR_OK == retval) + if (retval == ERROR_OK) command_print(CMD, "Greetings%s%s!", sep, name); return retval; } diff --git a/src/helper/command.c b/src/helper/command.c index 8ea805bd9..0c76450fa 100644 --- a/src/helper/command.c +++ b/src/helper/command.c @@ -394,11 +394,11 @@ int __register_commands(struct command_context *cmd_ctx, const char *cmd_prefix, } else { retval = __register_commands(cmd_ctx, cmd_prefix, cr->chain, data, override_target); } - if (ERROR_OK != retval) + if (retval != ERROR_OK) break; } } - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { for (unsigned j = 0; j < i; j++) unregister_command(cmd_ctx, cmd_prefix, cmds[j].name); } @@ -1171,7 +1171,7 @@ COMMAND_HANDLER(handle_sleep_command) unsigned long duration = 0; int retval = parse_ulong(CMD_ARGV[0], &duration); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (!busy) { @@ -1354,11 +1354,11 @@ void process_jim_events(struct command_context *cmd_ctx) LOG_ERROR("Invalid command argument"); \ return ERROR_COMMAND_ARGUMENT_INVALID; \ } \ - if ((max == *ul) && (ERANGE == errno)) { \ + if ((max == *ul) && (errno == ERANGE)) { \ LOG_ERROR("Argument overflow"); \ return ERROR_COMMAND_ARGUMENT_OVERFLOW; \ } \ - if (min && (min == *ul) && (ERANGE == errno)) { \ + if (min && (min == *ul) && (errno == ERANGE)) { \ LOG_ERROR("Argument underflow"); \ return ERROR_COMMAND_ARGUMENT_UNDERFLOW; \ } \ @@ -1374,7 +1374,7 @@ DEFINE_PARSE_NUM_TYPE(_llong, long long, strtoll, LLONG_MIN, LLONG_MAX) { \ functype n; \ int retval = parse ## funcname(str, &n); \ - if (ERROR_OK != retval) \ + if (retval != ERROR_OK) \ return retval; \ if (n > max) \ return ERROR_COMMAND_ARGUMENT_OVERFLOW; \ diff --git a/src/helper/command.h b/src/helper/command.h index 719c94b6b..f38701983 100644 --- a/src/helper/command.h +++ b/src/helper/command.h @@ -427,7 +427,7 @@ DECLARE_PARSE_WRAPPER(_target_addr, target_addr_t); #define COMMAND_PARSE_NUMBER(type, in, out) \ do { \ int retval_macro_tmp = parse_ ## type(in, &(out)); \ - if (ERROR_OK != retval_macro_tmp) { \ + if (retval_macro_tmp != ERROR_OK) { \ command_print(CMD, stringify(out) \ " option value ('%s') is not valid", in); \ return retval_macro_tmp; \ @@ -489,7 +489,7 @@ DECLARE_PARSE_WRAPPER(_target_addr, target_addr_t); do { \ bool value; \ int retval_macro_tmp = command_parse_bool_arg(in, &value); \ - if (ERROR_OK != retval_macro_tmp) { \ + if (retval_macro_tmp != ERROR_OK) { \ command_print(CMD, stringify(out) \ " option value ('%s') is not valid", in); \ command_print(CMD, " choices are '%s' or '%s'", \ diff --git a/src/helper/fileio.c b/src/helper/fileio.c index b6f1f4e2c..5138fa180 100644 --- a/src/helper/fileio.c +++ b/src/helper/fileio.c @@ -200,7 +200,7 @@ int fileio_read_u32(struct fileio *fileio, uint32_t *data) if (ERROR_OK == retval && sizeof(uint32_t) != size_read) retval = -EIO; - if (ERROR_OK == retval) + if (retval == ERROR_OK) *data = be_to_h_u32(buf); return retval; diff --git a/src/jtag/adapter.c b/src/jtag/adapter.c index a867d2c3c..b8b8f5a8f 100644 --- a/src/jtag/adapter.c +++ b/src/jtag/adapter.c @@ -120,7 +120,7 @@ COMMAND_HANDLER(handle_adapter_driver_command) if (NULL != adapter_drivers[i]->commands) { retval = register_commands(CMD_CTX, NULL, adapter_drivers[i]->commands); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; } @@ -394,13 +394,13 @@ COMMAND_HANDLER(handle_adapter_speed_command) COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], khz); retval = jtag_config_khz(khz); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; } int cur_speed = jtag_get_speed_khz(); retval = jtag_get_speed_readable(&cur_speed); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (cur_speed) diff --git a/src/jtag/aice/aice_transport.c b/src/jtag/aice/aice_transport.c index 7e06760fb..df399f816 100644 --- a/src/jtag/aice/aice_transport.c +++ b/src/jtag/aice/aice_transport.c @@ -119,7 +119,7 @@ static int jim_aice_newtap_cmd(struct jim_getopt_info *goi) switch (n->value) { case NTAP_OPT_EXPECTED_ID: e = jim_newtap_expected_id(n, goi, tap); - if (JIM_OK != e) { + if (e != JIM_OK) { free(cp); free(tap); return e; diff --git a/src/jtag/aice/aice_usb.c b/src/jtag/aice/aice_usb.c index 751fd135c..1c90b476c 100644 --- a/src/jtag/aice/aice_usb.c +++ b/src/jtag/aice/aice_usb.c @@ -360,9 +360,9 @@ static int usb_bulk_with_retries( int result, ret; ret = f(dev, ep, bytes + count, size - count, timeout, &result); - if (ERROR_OK == ret) + if (ret == ERROR_OK) count += result; - else if ((ERROR_TIMEOUT_REACHED != ret) || !--tries) + else if ((ret != ERROR_TIMEOUT_REACHED) || !--tries) return ret; } @@ -444,7 +444,7 @@ static int aice_usb_packet_flush(void) if (usb_out_packets_buffer_length == 0) return 0; - if (AICE_COMMAND_MODE_PACK == aice_command_mode) { + if (aice_command_mode == AICE_COMMAND_MODE_PACK) { LOG_DEBUG("Flush usb packets (AICE_COMMAND_MODE_PACK)"); if (aice_usb_write(usb_out_packets_buffer, @@ -458,7 +458,7 @@ static int aice_usb_packet_flush(void) usb_out_packets_buffer_length = 0; usb_in_packets_buffer_length = 0; - } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) { + } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { LOG_DEBUG("Flush usb packets (AICE_COMMAND_MODE_BATCH)"); /* use BATCH_BUFFER_WRITE to fill command-batch-buffer */ @@ -508,9 +508,9 @@ static int aice_usb_packet_append(uint8_t *out_buffer, int out_length, int in_le { uint32_t max_packet_size = AICE_OUT_PACKETS_BUFFER_SIZE; - if (AICE_COMMAND_MODE_PACK == aice_command_mode) { + if (aice_command_mode == AICE_COMMAND_MODE_PACK) { max_packet_size = AICE_OUT_PACK_COMMAND_SIZE; - } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) { + } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { max_packet_size = AICE_OUT_BATCH_COMMAND_SIZE; } else { /* AICE_COMMAND_MODE_NORMAL */ @@ -557,8 +557,8 @@ static int aice_scan_chain(uint32_t *id_codes, uint8_t *num_of_ids) { int retry_times = 0; - if ((AICE_COMMAND_MODE_PACK == aice_command_mode) || - (AICE_COMMAND_MODE_BATCH == aice_command_mode)) + if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || + (aice_command_mode == AICE_COMMAND_MODE_BATCH)) aice_usb_packet_flush(); do { @@ -570,7 +570,7 @@ static int aice_scan_chain(uint32_t *id_codes, uint8_t *num_of_ids) /** TODO: modify receive length */ int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHA); - if (AICE_FORMAT_DTHA != result) { + if (result != AICE_FORMAT_DTHA) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHA, result); return ERROR_FAIL; @@ -614,8 +614,8 @@ static int aice_scan_chain(uint32_t *id_codes, uint8_t *num_of_ids) int aice_read_ctrl(uint32_t address, uint32_t *data) { - if ((AICE_COMMAND_MODE_PACK == aice_command_mode) || - (AICE_COMMAND_MODE_BATCH == aice_command_mode)) + if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || + (aice_command_mode == AICE_COMMAND_MODE_BATCH)) aice_usb_packet_flush(); aice_pack_htda(AICE_CMD_READ_CTRL, 0, address); @@ -625,7 +625,7 @@ int aice_read_ctrl(uint32_t address, uint32_t *data) LOG_DEBUG("READ_CTRL, address: 0x%" PRIx32, address); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHA); - if (AICE_FORMAT_DTHA != result) { + if (result != AICE_FORMAT_DTHA) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHA, result); return ERROR_FAIL; @@ -648,9 +648,9 @@ int aice_read_ctrl(uint32_t address, uint32_t *data) int aice_write_ctrl(uint32_t address, uint32_t data) { - if (AICE_COMMAND_MODE_PACK == aice_command_mode) { + if (aice_command_mode == AICE_COMMAND_MODE_PACK) { aice_usb_packet_flush(); - } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) { + } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { aice_pack_htdc(AICE_CMD_WRITE_CTRL, 0, address, data, AICE_LITTLE_ENDIAN); return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDC, AICE_FORMAT_DTHB); @@ -663,7 +663,7 @@ int aice_write_ctrl(uint32_t address, uint32_t data) LOG_DEBUG("WRITE_CTRL, address: 0x%" PRIx32 ", data: 0x%" PRIx32, address, data); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHB); - if (AICE_FORMAT_DTHB != result) { + if (result != AICE_FORMAT_DTHB) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHB, result); return ERROR_FAIL; @@ -688,8 +688,8 @@ static int aice_read_dtr(uint8_t target_id, uint32_t *data) { int retry_times = 0; - if ((AICE_COMMAND_MODE_PACK == aice_command_mode) || - (AICE_COMMAND_MODE_BATCH == aice_command_mode)) + if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || + (aice_command_mode == AICE_COMMAND_MODE_BATCH)) aice_usb_packet_flush(); do { @@ -700,7 +700,7 @@ static int aice_read_dtr(uint8_t target_id, uint32_t *data) LOG_DEBUG("READ_DTR, COREID: %" PRIu8, target_id); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA); - if (AICE_FORMAT_DTHMA != result) { + if (result != AICE_FORMAT_DTHMA) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMA, result); return ERROR_FAIL; @@ -738,9 +738,9 @@ static int aice_read_dtr_to_buffer(uint8_t target_id, uint32_t buffer_idx) { int retry_times = 0; - if (AICE_COMMAND_MODE_PACK == aice_command_mode) { + if (aice_command_mode == AICE_COMMAND_MODE_PACK) { aice_usb_packet_flush(); - } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) { + } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { aice_pack_htdma(AICE_CMD_READ_DTR_TO_BUFFER, target_id, 0, buffer_idx); return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMA, AICE_FORMAT_DTHMB); @@ -754,7 +754,7 @@ static int aice_read_dtr_to_buffer(uint8_t target_id, uint32_t buffer_idx) LOG_DEBUG("READ_DTR_TO_BUFFER, COREID: %" PRIu8, target_id); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (AICE_FORMAT_DTHMB != result) { + if (result != AICE_FORMAT_DTHMB) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result); return ERROR_FAIL; } @@ -789,9 +789,9 @@ static int aice_write_dtr(uint8_t target_id, uint32_t data) { int retry_times = 0; - if (AICE_COMMAND_MODE_PACK == aice_command_mode) { + if (aice_command_mode == AICE_COMMAND_MODE_PACK) { aice_usb_packet_flush(); - } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) { + } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { aice_pack_htdmc(AICE_CMD_T_WRITE_DTR, target_id, 0, 0, data, AICE_LITTLE_ENDIAN); return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMC, AICE_FORMAT_DTHMB); @@ -805,7 +805,7 @@ static int aice_write_dtr(uint8_t target_id, uint32_t data) LOG_DEBUG("WRITE_DTR, COREID: %" PRIu8 ", data: 0x%" PRIx32, target_id, data); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (AICE_FORMAT_DTHMB != result) { + if (result != AICE_FORMAT_DTHMB) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result); return ERROR_FAIL; } @@ -841,9 +841,9 @@ static int aice_write_dtr_from_buffer(uint8_t target_id, uint32_t buffer_idx) { int retry_times = 0; - if (AICE_COMMAND_MODE_PACK == aice_command_mode) { + if (aice_command_mode == AICE_COMMAND_MODE_PACK) { aice_usb_packet_flush(); - } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) { + } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { aice_pack_htdma(AICE_CMD_WRITE_DTR_FROM_BUFFER, target_id, 0, buffer_idx); return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMA, AICE_FORMAT_DTHMB); @@ -857,7 +857,7 @@ static int aice_write_dtr_from_buffer(uint8_t target_id, uint32_t buffer_idx) LOG_DEBUG("WRITE_DTR_FROM_BUFFER, COREID: %" PRIu8 "", target_id); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (AICE_FORMAT_DTHMB != result) { + if (result != AICE_FORMAT_DTHMB) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result); return ERROR_FAIL; } @@ -892,8 +892,8 @@ static int aice_read_misc(uint8_t target_id, uint32_t address, uint32_t *data) { int retry_times = 0; - if ((AICE_COMMAND_MODE_PACK == aice_command_mode) || - (AICE_COMMAND_MODE_BATCH == aice_command_mode)) + if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || + (aice_command_mode == AICE_COMMAND_MODE_BATCH)) aice_usb_packet_flush(); do { @@ -904,7 +904,7 @@ static int aice_read_misc(uint8_t target_id, uint32_t address, uint32_t *data) LOG_DEBUG("READ_MISC, COREID: %" PRIu8 ", address: 0x%" PRIx32, target_id, address); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA); - if (AICE_FORMAT_DTHMA != result) { + if (result != AICE_FORMAT_DTHMA) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMA, result); return ERROR_AICE_DISCONNECT; @@ -941,9 +941,9 @@ static int aice_write_misc(uint8_t target_id, uint32_t address, uint32_t data) { int retry_times = 0; - if (AICE_COMMAND_MODE_PACK == aice_command_mode) { + if (aice_command_mode == AICE_COMMAND_MODE_PACK) { aice_usb_packet_flush(); - } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) { + } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { aice_pack_htdmc(AICE_CMD_T_WRITE_MISC, target_id, 0, address, data, AICE_LITTLE_ENDIAN); return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMC, @@ -960,7 +960,7 @@ static int aice_write_misc(uint8_t target_id, uint32_t address, uint32_t data) target_id, address, data); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (AICE_FORMAT_DTHMB != result) { + if (result != AICE_FORMAT_DTHMB) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result); return ERROR_FAIL; @@ -997,8 +997,8 @@ static int aice_read_edmsr(uint8_t target_id, uint32_t address, uint32_t *data) { int retry_times = 0; - if ((AICE_COMMAND_MODE_PACK == aice_command_mode) || - (AICE_COMMAND_MODE_BATCH == aice_command_mode)) + if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || + (aice_command_mode == AICE_COMMAND_MODE_BATCH)) aice_usb_packet_flush(); do { @@ -1009,7 +1009,7 @@ static int aice_read_edmsr(uint8_t target_id, uint32_t address, uint32_t *data) LOG_DEBUG("READ_EDMSR, COREID: %" PRIu8 ", address: 0x%" PRIx32, target_id, address); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA); - if (AICE_FORMAT_DTHMA != result) { + if (result != AICE_FORMAT_DTHMA) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMA, result); return ERROR_FAIL; @@ -1047,9 +1047,9 @@ static int aice_write_edmsr(uint8_t target_id, uint32_t address, uint32_t data) { int retry_times = 0; - if (AICE_COMMAND_MODE_PACK == aice_command_mode) { + if (aice_command_mode == AICE_COMMAND_MODE_PACK) { aice_usb_packet_flush(); - } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) { + } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { aice_pack_htdmc(AICE_CMD_T_WRITE_EDMSR, target_id, 0, address, data, AICE_LITTLE_ENDIAN); return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMC, @@ -1066,7 +1066,7 @@ static int aice_write_edmsr(uint8_t target_id, uint32_t address, uint32_t data) target_id, address, data); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (AICE_FORMAT_DTHMB != result) { + if (result != AICE_FORMAT_DTHMB) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result); return ERROR_FAIL; @@ -1123,9 +1123,9 @@ static int aice_write_dim(uint8_t target_id, uint32_t *word, uint8_t num_of_word memcpy(big_endian_word, word, sizeof(big_endian_word)); aice_switch_to_big_endian(big_endian_word, num_of_words); - if (AICE_COMMAND_MODE_PACK == aice_command_mode) { + if (aice_command_mode == AICE_COMMAND_MODE_PACK) { aice_usb_packet_flush(); - } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) { + } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { aice_pack_htdmc_multiple_data(AICE_CMD_T_WRITE_DIM, target_id, num_of_words - 1, 0, big_endian_word, num_of_words, AICE_LITTLE_ENDIAN); @@ -1149,7 +1149,7 @@ static int aice_write_dim(uint8_t target_id, uint32_t *word, uint8_t num_of_word big_endian_word[3]); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (AICE_FORMAT_DTHMB != result) { + if (result != AICE_FORMAT_DTHMB) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result); return ERROR_FAIL; } @@ -1187,9 +1187,9 @@ static int aice_do_execute(uint8_t target_id) { int retry_times = 0; - if (AICE_COMMAND_MODE_PACK == aice_command_mode) { + if (aice_command_mode == AICE_COMMAND_MODE_PACK) { aice_usb_packet_flush(); - } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) { + } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { aice_pack_htdmc(AICE_CMD_T_EXECUTE, target_id, 0, 0, 0, AICE_LITTLE_ENDIAN); return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMC, @@ -1204,7 +1204,7 @@ static int aice_do_execute(uint8_t target_id) LOG_DEBUG("EXECUTE, COREID: %" PRIu8 "", target_id); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (AICE_FORMAT_DTHMB != result) { + if (result != AICE_FORMAT_DTHMB) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result); return ERROR_FAIL; @@ -1246,8 +1246,8 @@ static int aice_write_mem_b(uint8_t target_id, uint32_t address, uint32_t data) address, data); - if ((AICE_COMMAND_MODE_PACK == aice_command_mode) || - (AICE_COMMAND_MODE_BATCH == aice_command_mode)) { + if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || + (aice_command_mode == AICE_COMMAND_MODE_BATCH)) { aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B, target_id, 0, address, data & 0x000000FF, data_endian); return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMD, @@ -1259,7 +1259,7 @@ static int aice_write_mem_b(uint8_t target_id, uint32_t address, uint32_t data) aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (AICE_FORMAT_DTHMB != result) { + if (result != AICE_FORMAT_DTHMB) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result); return ERROR_FAIL; } @@ -1300,8 +1300,8 @@ static int aice_write_mem_h(uint8_t target_id, uint32_t address, uint32_t data) address, data); - if ((AICE_COMMAND_MODE_PACK == aice_command_mode) || - (AICE_COMMAND_MODE_BATCH == aice_command_mode)) { + if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || + (aice_command_mode == AICE_COMMAND_MODE_BATCH)) { aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H, target_id, 0, (address >> 1) & 0x7FFFFFFF, data & 0x0000FFFF, data_endian); return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMD, @@ -1313,7 +1313,7 @@ static int aice_write_mem_h(uint8_t target_id, uint32_t address, uint32_t data) aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (AICE_FORMAT_DTHMB != result) { + if (result != AICE_FORMAT_DTHMB) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result); return ERROR_FAIL; @@ -1355,8 +1355,8 @@ static int aice_write_mem(uint8_t target_id, uint32_t address, uint32_t data) address, data); - if ((AICE_COMMAND_MODE_PACK == aice_command_mode) || - (AICE_COMMAND_MODE_BATCH == aice_command_mode)) { + if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || + (aice_command_mode == AICE_COMMAND_MODE_BATCH)) { aice_pack_htdmd(AICE_CMD_T_WRITE_MEM, target_id, 0, (address >> 2) & 0x3FFFFFFF, data, data_endian); return aice_usb_packet_append(usb_out_buffer, AICE_FORMAT_HTDMD, @@ -1368,7 +1368,7 @@ static int aice_write_mem(uint8_t target_id, uint32_t address, uint32_t data) aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (AICE_FORMAT_DTHMB != result) { + if (result != AICE_FORMAT_DTHMB) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result); return ERROR_FAIL; @@ -1405,8 +1405,8 @@ static int aice_fastread_mem(uint8_t target_id, uint8_t *word, uint32_t num_of_w { int retry_times = 0; - if ((AICE_COMMAND_MODE_PACK == aice_command_mode) || - (AICE_COMMAND_MODE_BATCH == aice_command_mode)) + if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || + (aice_command_mode == AICE_COMMAND_MODE_BATCH)) aice_usb_packet_flush(); do { @@ -1455,9 +1455,9 @@ static int aice_fastwrite_mem(uint8_t target_id, const uint8_t *word, uint32_t n { int retry_times = 0; - if (AICE_COMMAND_MODE_PACK == aice_command_mode) { + if (aice_command_mode == AICE_COMMAND_MODE_PACK) { aice_usb_packet_flush(); - } else if (AICE_COMMAND_MODE_BATCH == aice_command_mode) { + } else if (aice_command_mode == AICE_COMMAND_MODE_BATCH) { aice_pack_htdmd_multiple_data(AICE_CMD_T_FASTWRITE_MEM, target_id, num_of_words - 1, 0, word, data_endian); return aice_usb_packet_append(usb_out_buffer, @@ -1475,7 +1475,7 @@ static int aice_fastwrite_mem(uint8_t target_id, const uint8_t *word, uint32_t n target_id, num_of_words); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (AICE_FORMAT_DTHMB != result) { + if (result != AICE_FORMAT_DTHMB) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result); return ERROR_FAIL; @@ -1511,8 +1511,8 @@ static int aice_read_mem_b(uint8_t target_id, uint32_t address, uint32_t *data) { int retry_times = 0; - if ((AICE_COMMAND_MODE_PACK == aice_command_mode) || - (AICE_COMMAND_MODE_BATCH == aice_command_mode)) + if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || + (aice_command_mode == AICE_COMMAND_MODE_BATCH)) aice_usb_packet_flush(); do { @@ -1523,7 +1523,7 @@ static int aice_read_mem_b(uint8_t target_id, uint32_t address, uint32_t *data) LOG_DEBUG("READ_MEM_B, COREID: %" PRIu8 "", target_id); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA); - if (AICE_FORMAT_DTHMA != result) { + if (result != AICE_FORMAT_DTHMA) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMA, result); return ERROR_FAIL; @@ -1561,8 +1561,8 @@ static int aice_read_mem_h(uint8_t target_id, uint32_t address, uint32_t *data) { int retry_times = 0; - if ((AICE_COMMAND_MODE_PACK == aice_command_mode) || - (AICE_COMMAND_MODE_BATCH == aice_command_mode)) + if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || + (aice_command_mode == AICE_COMMAND_MODE_BATCH)) aice_usb_packet_flush(); do { @@ -1573,7 +1573,7 @@ static int aice_read_mem_h(uint8_t target_id, uint32_t address, uint32_t *data) LOG_DEBUG("READ_MEM_H, CORE_ID: %" PRIu8 "", target_id); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA); - if (AICE_FORMAT_DTHMA != result) { + if (result != AICE_FORMAT_DTHMA) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMA, result); return ERROR_FAIL; @@ -1611,8 +1611,8 @@ static int aice_read_mem(uint8_t target_id, uint32_t address, uint32_t *data) { int retry_times = 0; - if ((AICE_COMMAND_MODE_PACK == aice_command_mode) || - (AICE_COMMAND_MODE_BATCH == aice_command_mode)) + if ((aice_command_mode == AICE_COMMAND_MODE_PACK) || + (aice_command_mode == AICE_COMMAND_MODE_BATCH)) aice_usb_packet_flush(); do { @@ -1624,7 +1624,7 @@ static int aice_read_mem(uint8_t target_id, uint32_t address, uint32_t *data) LOG_DEBUG("READ_MEM, COREID: %" PRIu8 "", target_id); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA); - if (AICE_FORMAT_DTHMA != result) { + if (result != AICE_FORMAT_DTHMA) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMA, result); return ERROR_FAIL; @@ -1723,7 +1723,7 @@ int aice_batch_buffer_write(uint8_t buf_index, const uint8_t *word, uint32_t num LOG_DEBUG("BATCH_BUFFER_WRITE, # of DATA %08" PRIx32, num_of_words); int result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB); - if (AICE_FORMAT_DTHMB != result) { + if (result != AICE_FORMAT_DTHMB) { LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB, result); return ERROR_FAIL; @@ -1918,12 +1918,12 @@ static int aice_read_reg(uint32_t coreid, uint32_t num, uint32_t *val) instructions[3] = BEQ_MINUS_12; } } else if (NDS32_REG_TYPE_FPU == nds32_reg_type(num)) { /* fpu registers */ - if (FPCSR == num) { + if (num == FPCSR) { instructions[0] = FMFCSR; instructions[1] = MTSR_DTR(0); instructions[2] = DSB; instructions[3] = BEQ_MINUS_12; - } else if (FPCFG == num) { + } else if (num == FPCFG) { instructions[0] = FMFCFG; instructions[1] = MTSR_DTR(0); instructions[2] = DSB; @@ -2027,12 +2027,12 @@ static int aice_write_reg(uint32_t coreid, uint32_t num, uint32_t val) instructions[3] = BEQ_MINUS_12; } } else if (NDS32_REG_TYPE_FPU == nds32_reg_type(num)) { /* fpu registers */ - if (FPCSR == num) { + if (num == FPCSR) { instructions[0] = MFSR_DTR(0); instructions[1] = FMTCSR; instructions[2] = DSB; instructions[3] = BEQ_MINUS_12; - } else if (FPCFG == num) { + } else if (num == FPCFG) { /* FPCFG is readonly */ } else { if (FS0 <= num && num <= FS31) { /* single precision */ @@ -2116,7 +2116,7 @@ static int aice_usb_open(struct aice_port_param_s *param) if (!timeout) break; } - if (ERROR_OK != retval) + if (retval != ERROR_OK) return ERROR_FAIL; #endif @@ -2558,7 +2558,7 @@ static int aice_usb_idcode(uint32_t *idcode, uint8_t *num_of_idcode) int retval; retval = aice_scan_chain(idcode, num_of_idcode); - if (ERROR_OK == retval) { + if (retval == ERROR_OK) { for (int i = 0; i < *num_of_idcode; i++) { aice_core_init(i); aice_edm_init(i); @@ -2659,7 +2659,7 @@ static int aice_usb_state(uint32_t coreid, enum aice_target_state_s *state) int result = aice_read_misc(coreid, NDS_EDM_MISC_DBGER, &dbger_value); - if (ERROR_AICE_TIMEOUT == result) { + if (result == ERROR_AICE_TIMEOUT) { if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE, &ice_state) != ERROR_OK) { LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->"); return ERROR_FAIL; @@ -2671,7 +2671,7 @@ static int aice_usb_state(uint32_t coreid, enum aice_target_state_s *state) } else { return ERROR_FAIL; } - } else if (ERROR_AICE_DISCONNECT == result) { + } else if (result == ERROR_AICE_DISCONNECT) { LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->"); return ERROR_FAIL; } @@ -2877,7 +2877,7 @@ static int aice_issue_reset_hold_multi(void) static int aice_usb_assert_srst(uint32_t coreid, enum aice_srst_type_s srst) { - if ((AICE_SRST != srst) && (AICE_RESET_HOLD != srst)) + if ((srst != AICE_SRST) && (srst != AICE_RESET_HOLD)) return ERROR_FAIL; /* clear DBGER */ @@ -2886,7 +2886,7 @@ static int aice_usb_assert_srst(uint32_t coreid, enum aice_srst_type_s srst) return ERROR_FAIL; int result = ERROR_OK; - if (AICE_SRST == srst) + if (srst == AICE_SRST) result = aice_issue_srst(coreid); else { if (1 == total_num_of_core) @@ -2982,7 +2982,7 @@ static int aice_usb_step(uint32_t coreid) if (aice_usb_state(coreid, &state) != ERROR_OK) return ERROR_FAIL; - if (AICE_TARGET_HALTED == state) + if (state == AICE_TARGET_HALTED) break; int64_t then = 0; @@ -3354,9 +3354,9 @@ static int aice_usb_bulk_write_mem(uint32_t coreid, uint32_t addr, static int aice_usb_read_debug_reg(uint32_t coreid, uint32_t addr, uint32_t *val) { if (AICE_TARGET_HALTED == core_info[coreid].core_state) { - if (NDS_EDM_SR_EDMSW == addr) { + if (addr == NDS_EDM_SR_EDMSW) { *val = core_info[coreid].edmsw_backup; - } else if (NDS_EDM_SR_EDM_DTR == addr) { + } else if (addr == NDS_EDM_SR_EDM_DTR) { if (core_info[coreid].target_dtr_valid) { /* if EDM_DTR has read out, clear it. */ *val = core_info[coreid].target_dtr_backup; @@ -3374,7 +3374,7 @@ static int aice_usb_read_debug_reg(uint32_t coreid, uint32_t addr, uint32_t *val static int aice_usb_write_debug_reg(uint32_t coreid, uint32_t addr, const uint32_t val) { if (AICE_TARGET_HALTED == core_info[coreid].core_state) { - if (NDS_EDM_SR_EDM_DTR == addr) { + if (addr == NDS_EDM_SR_EDM_DTR) { core_info[coreid].host_dtr_backup = val; core_info[coreid].edmsw_backup |= 0x2; core_info[coreid].host_dtr_valid = true; @@ -3775,7 +3775,7 @@ static int aice_usb_set_command_mode(enum aice_command_mode command_mode) /* flush usb_packets_buffer as users change mode */ retval = aice_usb_packet_flush(); - if (AICE_COMMAND_MODE_BATCH == command_mode) { + if (command_mode == AICE_COMMAND_MODE_BATCH) { /* reset batch buffer */ aice_command_mode = AICE_COMMAND_MODE_NORMAL; retval = aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CMD_BUF0_CTRL, 0x40000); diff --git a/src/jtag/core.c b/src/jtag/core.c index 456faf7a9..4b902ca70 100644 --- a/src/jtag/core.c +++ b/src/jtag/core.c @@ -1533,7 +1533,7 @@ int adapter_init(struct command_context *cmd_ctx) return ERROR_OK; } - if (CLOCK_MODE_UNSELECTED == clock_mode) { + if (clock_mode == CLOCK_MODE_UNSELECTED) { LOG_ERROR("An adapter speed is not selected in the init script." " Insert a call to \"adapter speed\" or \"jtag_rclk\" to proceed."); return ERROR_JTAG_INIT_FAILED; @@ -1549,12 +1549,12 @@ int adapter_init(struct command_context *cmd_ctx) if (retval != ERROR_OK) return retval; retval = jtag_get_speed_readable(&actual_khz); - if (ERROR_OK != retval) + if (retval != ERROR_OK) LOG_INFO("adapter-specific clock speed value %d", jtag_speed_var); else if (actual_khz) { /* Adaptive clocking -- JTAG-specific */ - if ((CLOCK_MODE_RCLK == clock_mode) - || ((CLOCK_MODE_KHZ == clock_mode) && !requested_khz)) { + if ((clock_mode == CLOCK_MODE_RCLK) + || ((clock_mode == CLOCK_MODE_KHZ) && !requested_khz)) { LOG_INFO("RCLK (adaptive clock speed) not supported - fallback to %d kHz" , actual_khz); } else @@ -1650,7 +1650,7 @@ int adapter_quit(void) if (jtag && jtag->quit) { /* close the JTAG interface */ int result = jtag->quit(); - if (ERROR_OK != result) + if (result != ERROR_OK) LOG_ERROR("failed: %d", result); } @@ -1789,7 +1789,7 @@ static int adapter_khz_to_speed(unsigned khz, int *speed) } int speed_div1; int retval = jtag->khz(jtag_get_speed_khz(), &speed_div1); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; *speed = speed_div1; return ERROR_OK; @@ -1798,7 +1798,7 @@ static int adapter_khz_to_speed(unsigned khz, int *speed) static int jtag_rclk_to_speed(unsigned fallback_speed_khz, int *speed) { int retval = adapter_khz_to_speed(0, speed); - if ((ERROR_OK != retval) && fallback_speed_khz) { + if ((retval != ERROR_OK) && fallback_speed_khz) { LOG_DEBUG("trying fallback speed..."); retval = adapter_khz_to_speed(fallback_speed_khz, speed); } @@ -1819,7 +1819,7 @@ int jtag_config_khz(unsigned khz) clock_mode = CLOCK_MODE_KHZ; int speed = 0; int retval = adapter_khz_to_speed(khz, &speed); - return (ERROR_OK != retval) ? retval : jtag_set_speed(speed); + return (retval != ERROR_OK) ? retval : jtag_set_speed(speed); } int jtag_config_rclk(unsigned fallback_speed_khz) @@ -1829,7 +1829,7 @@ int jtag_config_rclk(unsigned fallback_speed_khz) rclk_fallback_speed_khz = fallback_speed_khz; int speed = 0; int retval = jtag_rclk_to_speed(fallback_speed_khz, &speed); - return (ERROR_OK != retval) ? retval : jtag_set_speed(speed); + return (retval != ERROR_OK) ? retval : jtag_set_speed(speed); } int jtag_get_speed(int *speed) diff --git a/src/jtag/drivers/parport.c b/src/jtag/drivers/parport.c index b203c828b..e61b20b3a 100644 --- a/src/jtag/drivers/parport.c +++ b/src/jtag/drivers/parport.c @@ -448,7 +448,7 @@ COMMAND_HANDLER(parport_handle_parport_toggling_time_command) uint32_t ns; int retval = parse_u32(CMD_ARGV[0], &ns); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (ns == 0) { diff --git a/src/jtag/drivers/versaloon/versaloon.c b/src/jtag/drivers/versaloon/versaloon.c index e564d8b46..b8602ddeb 100644 --- a/src/jtag/drivers/versaloon/versaloon.c +++ b/src/jtag/drivers/versaloon/versaloon.c @@ -258,7 +258,7 @@ static RESULT versaloon_init(void) break; } versaloon_usb_to = timeout_tmp; - if (VERSALOON_RETRY_CNT == retry) { + if (retry == VERSALOON_RETRY_CNT) { versaloon_fini(); LOG_ERROR(ERRMSG_FAILURE_OPERATION, "communicate with versaloon"); return ERRCODE_FAILURE_OPERATION; diff --git a/src/jtag/drivers/vsllink.c b/src/jtag/drivers/vsllink.c index f08fa9165..6a592bcfb 100644 --- a/src/jtag/drivers/vsllink.c +++ b/src/jtag/drivers/vsllink.c @@ -310,7 +310,7 @@ static int vsllink_interface_init(void) static int vsllink_init(void) { int retval = vsllink_interface_init(); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; versaloon_interface.adaptors.gpio.init(0); @@ -838,7 +838,7 @@ static int vsllink_usb_open(struct vsllink *vsllink) continue; retval = vsllink_check_usb_strings(usb_device_handle, &usb_desc); - if (ERROR_OK == retval) + if (retval == ERROR_OK) break; libusb_close(usb_device_handle); diff --git a/src/jtag/drivers/xds110.c b/src/jtag/drivers/xds110.c index 23a431cf7..7b560df9d 100644 --- a/src/jtag/drivers/xds110.c +++ b/src/jtag/drivers/xds110.c @@ -661,7 +661,7 @@ static bool xds_execute(uint32_t out_length, uint32_t in_length, /* Extract error code from return packet */ error = (int)xds110_get_u32(&xds110.read_payload[0]); done = true; - if (SC_ERR_NONE != error) + if (error != SC_ERR_NONE) LOG_DEBUG("XDS110: command 0x%02x returned error %d", xds110.write_payload[0], error); } @@ -1183,7 +1183,7 @@ static bool xds110_legacy_read_reg(uint8_t cmd, uint32_t *value) if (!is_read_request) return false; - if (DAP_AP == type) { + if (type == DAP_AP) { /* Add bank address to register address for CMAPI call */ address |= bank; } @@ -1245,12 +1245,12 @@ static bool xds110_legacy_write_reg(uint8_t cmd, uint32_t value) /* Invalidate the RDBUFF cache */ xds110.use_rdbuff = false; - if (DAP_AP == type) { + if (type == DAP_AP) { /* Add bank address to register address for CMAPI call */ address |= bank; /* Any write to an AP register invalidates the firmware's cache */ xds110.is_ap_dirty = true; - } else if (DAP_DP_SELECT == address) { + } else if (address == DAP_DP_SELECT) { /* Any write to the SELECT register invalidates the firmware's cache */ xds110.is_ap_dirty = true; } @@ -1264,7 +1264,7 @@ static bool xds110_legacy_write_reg(uint8_t cmd, uint32_t value) * If the debugger wrote to SELECT, cache the value * to use to build the apNum and address values above */ - if ((DAP_DP == type) && (DAP_DP_SELECT == address)) + if ((type == DAP_DP) && (address == DAP_DP_SELECT)) xds110.select = value; } diff --git a/src/jtag/hla/hla_tcl.c b/src/jtag/hla/hla_tcl.c index bd26ec54e..5aa330145 100644 --- a/src/jtag/hla/hla_tcl.c +++ b/src/jtag/hla/hla_tcl.c @@ -122,7 +122,7 @@ static int jim_hl_newtap_cmd(struct jim_getopt_info *goi) switch (n->value) { case NTAP_OPT_EXPECTED_ID: e = jim_newtap_expected_id(n, goi, tap); - if (JIM_OK != e) { + if (e != JIM_OK) { free(cp); free(tap); return e; diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c index b765305e5..79eea5460 100644 --- a/src/jtag/tcl.c +++ b/src/jtag/tcl.c @@ -597,7 +597,7 @@ static int jim_newtap_cmd(struct jim_getopt_info *goi) break; case NTAP_OPT_EXPECTED_ID: e = jim_newtap_expected_id(n, goi, tap); - if (JIM_OK != e) { + if (e != JIM_OK) { free(cp); free(tap); return e; @@ -607,7 +607,7 @@ static int jim_newtap_cmd(struct jim_getopt_info *goi) case NTAP_OPT_IRMASK: case NTAP_OPT_IRCAPTURE: e = jim_newtap_ir_param(n, goi, tap); - if (JIM_OK != e) { + if (e != JIM_OK) { free(cp); free(tap); return e; @@ -1041,13 +1041,13 @@ COMMAND_HANDLER(handle_jtag_rclk_command) COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], khz); retval = jtag_config_rclk(khz); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; } int cur_khz = jtag_get_speed_khz(); retval = jtag_get_speed_readable(&cur_khz); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (cur_khz) @@ -1130,7 +1130,7 @@ COMMAND_HANDLER(handle_irscan_command) } uint64_t value; retval = parse_u64(CMD_ARGV[i * 2 + 1], &value); - if (ERROR_OK != retval) + if (retval != ERROR_OK) goto error_return; int field_size = tap->ir_length; diff --git a/src/openocd.c b/src/openocd.c index 32b68b6fc..2eb7346c5 100644 --- a/src/openocd.c +++ b/src/openocd.c @@ -131,7 +131,7 @@ COMMAND_HANDLER(handle_init_command) initialized = 1; retval = command_run_line(CMD_CTX, "target init"); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return ERROR_FAIL; retval = adapter_init(CMD_CTX); @@ -150,11 +150,11 @@ COMMAND_HANDLER(handle_init_command) command_context_mode(CMD_CTX, COMMAND_EXEC); retval = command_run_line(CMD_CTX, "transport init"); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return ERROR_FAIL; retval = command_run_line(CMD_CTX, "dap init"); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return ERROR_FAIL; LOG_DEBUG("Examining targets..."); @@ -264,7 +264,7 @@ static struct command_context *setup_command_handler(Jim_Interp *interp) }; for (unsigned i = 0; NULL != command_registrants[i]; i++) { int retval = (*command_registrants[i])(cmd_ctx); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { command_done(cmd_ctx); return NULL; } @@ -303,12 +303,12 @@ static int openocd_thread(int argc, char *argv[], struct command_context *cmd_ct } ret = server_init(cmd_ctx); - if (ERROR_OK != ret) + if (ret != ERROR_OK) return ERROR_FAIL; if (init_at_startup) { ret = command_run_line(cmd_ctx, "init"); - if (ERROR_OK != ret) { + if (ret != ERROR_OK) { server_quit(); return ERROR_FAIL; } @@ -377,9 +377,9 @@ int openocd_main(int argc, char *argv[]) rtt_exit(); free_config(); - if (ERROR_FAIL == ret) + if (ret == ERROR_FAIL) return EXIT_FAILURE; - else if (ERROR_OK != ret) + else if (ret != ERROR_OK) exit_on_signal(ret); return ret; diff --git a/src/pld/pld.c b/src/pld/pld.c index 66f5d44bc..d0f85d74b 100644 --- a/src/pld/pld.c +++ b/src/pld/pld.c @@ -69,7 +69,7 @@ COMMAND_HANDLER(handle_pld_device_command) if (pld_drivers[i]->commands) { retval = register_commands(CMD_CTX, NULL, pld_drivers[i]->commands); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("couldn't register '%s' commands", CMD_ARGV[0]); return ERROR_FAIL; } @@ -81,7 +81,7 @@ COMMAND_HANDLER(handle_pld_device_command) retval = CALL_COMMAND_HANDLER( pld_drivers[i]->pld_device_command, c); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("'%s' driver rejected pld device", CMD_ARGV[0]); free(c); diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c index 2bc8910c2..8e3febc06 100644 --- a/src/rtos/rtos.c +++ b/src/rtos/rtos.c @@ -113,7 +113,7 @@ static int os_alloc_create(struct target *target, struct rtos_type *ostype) { int ret = os_alloc(target, ostype); - if (JIM_OK == ret) { + if (ret == JIM_OK) { ret = target->rtos->type->create(target); if (ret != JIM_OK) os_free(target); diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c index 9ac982f6c..2853f05d9 100644 --- a/src/server/gdb_server.c +++ b/src/server/gdb_server.c @@ -3622,7 +3622,7 @@ int gdb_target_add_all(struct target *target) while (NULL != target) { int retval = gdb_target_add_one(target); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; target = target->next; @@ -3651,7 +3651,7 @@ COMMAND_HANDLER(handle_gdb_sync_command) COMMAND_HANDLER(handle_gdb_port_command) { int retval = CALL_COMMAND_HANDLER(server_pipe_command, &gdb_port); - if (ERROR_OK == retval) { + if (retval == ERROR_OK) { free(gdb_port_next); gdb_port_next = strdup(gdb_port); } diff --git a/src/server/server.c b/src/server/server.c index ebf88981b..5f18efce3 100644 --- a/src/server/server.c +++ b/src/server/server.c @@ -819,15 +819,15 @@ static const struct command_registration server_command_handlers[] = { int server_register_commands(struct command_context *cmd_ctx) { int retval = telnet_register_commands(cmd_ctx); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = tcl_register_commands(cmd_ctx); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = jsp_register_commands(cmd_ctx); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; return register_commands(cmd_ctx, NULL, server_command_handlers); diff --git a/src/svf/svf.c b/src/svf/svf.c index 482dcdc0d..10ad7e713 100644 --- a/src/svf/svf.c +++ b/src/svf/svf.c @@ -569,7 +569,7 @@ free_all: svf_free_xxd_para(&svf_para.sdr_para); svf_free_xxd_para(&svf_para.sir_para); - if (ERROR_OK == ret) + if (ret == ERROR_OK) command_print(CMD, "svf file programmed %s for %d commands with %d errors", (svf_ignore_error > 1) ? "unsuccessfully" : "successfully", @@ -742,8 +742,8 @@ parse_char: bool svf_tap_state_is_stable(tap_state_t state) { - return (TAP_RESET == state) || (TAP_IDLE == state) - || (TAP_DRPAUSE == state) || (TAP_IRPAUSE == state); + return (state == TAP_RESET) || (state == TAP_IDLE) + || (state == TAP_DRPAUSE) || (state == TAP_IRPAUSE); } static int svf_find_string_in_array(char *str, char **strs, int num_of_element) @@ -1110,7 +1110,7 @@ xxr_common: memset(xxr_para_tmp->mask, 0, (xxr_para_tmp->len + 7) >> 3); } /* do scan if necessary */ - if (SDR == command) { + if (command == SDR) { /* check buffer size first, reallocate if necessary */ i = svf_para.hdr_para.len + svf_para.sdr_para.len + svf_para.tdr_para.len; @@ -1201,7 +1201,7 @@ xxr_common: } svf_buffer_index += (i + 7) >> 3; - } else if (SIR == command) { + } else if (command == SIR) { /* check buffer size first, reallocate if necessary */ i = svf_para.hir_para.len + svf_para.sir_para.len + svf_para.tir_para.len; @@ -1534,9 +1534,8 @@ xxr_common: return ERROR_FAIL; /* output debug info */ - if ((SIR == command) || (SDR == command)) { + if ((command == SIR) || (command == SDR)) SVF_BUF_LOG(DEBUG, svf_tdi_buffer, svf_check_tdo_para[0].bit_len, "TDO read"); - } } } else { /* for fast executing, execute tap if necessary */ diff --git a/src/target/arc.c b/src/target/arc.c index e11cd7d79..77c9090f0 100644 --- a/src/target/arc.c +++ b/src/target/arc.c @@ -866,7 +866,7 @@ static int arc_save_context(struct target *target) /* Read data from target. */ if (core_cnt > 0) { retval = arc_jtag_read_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Attempt to read core registers failed."); retval = ERROR_FAIL; goto exit; @@ -874,7 +874,7 @@ static int arc_save_context(struct target *target) } if (aux_cnt > 0) { retval = arc_jtag_read_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Attempt to read aux registers failed."); retval = ERROR_FAIL; goto exit; @@ -1197,7 +1197,7 @@ static int arc_restore_context(struct target *target) * Check before write, if aux and core count is greater than 0. */ if (core_cnt > 0) { retval = arc_jtag_write_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Attempt to write to core registers failed."); retval = ERROR_FAIL; goto exit; @@ -1206,7 +1206,7 @@ static int arc_restore_context(struct target *target) if (aux_cnt > 0) { retval = arc_jtag_write_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("Attempt to write to aux registers failed."); retval = ERROR_FAIL; goto exit; diff --git a/src/target/arc_mem.c b/src/target/arc_mem.c index 96762690f..81d1ab277 100644 --- a/src/target/arc_mem.c +++ b/src/target/arc_mem.c @@ -281,7 +281,7 @@ int arc_mem_read(struct target *target, target_addr_t address, uint32_t size, /* arc_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */ /* endianness, but byte array should represent target endianness */ - if (ERROR_OK == retval) { + if (retval == ERROR_OK) { switch (size) { case 4: target_buffer_set_u32_array(target, buffer, count, diff --git a/src/target/arm_cti.c b/src/target/arm_cti.c index 30212cbf4..c168245a2 100644 --- a/src/target/arm_cti.c +++ b/src/target/arm_cti.c @@ -70,7 +70,7 @@ static int arm_cti_mod_reg_bits(struct arm_cti *self, unsigned int reg, uint32_t /* Read register */ int retval = mem_ap_read_atomic_u32(ap, self->spot.base + reg, &tmp); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* clear bitfield */ @@ -508,7 +508,7 @@ static int cti_create(struct jim_getopt_info *goi) COMMAND_REGISTRATION_DONE }; e = register_commands_with_data(cmd_ctx, NULL, cti_commands, cti); - if (ERROR_OK != e) + if (e != ERROR_OK) return JIM_ERR; list_add_tail(&cti->lh, &all_cti); diff --git a/src/target/arm_dap.c b/src/target/arm_dap.c index 87e232af8..68297b956 100644 --- a/src/target/arm_dap.c +++ b/src/target/arm_dap.c @@ -269,7 +269,7 @@ static int dap_create(struct jim_getopt_info *goi) dap_commands[0].chain = NULL; e = register_commands_with_data(cmd_ctx, NULL, dap_commands, dap); - if (ERROR_OK != e) + if (e != ERROR_OK) return JIM_ERR; list_add_tail(&dap->lh, &all_dap); diff --git a/src/target/arm_tpiu_swo.c b/src/target/arm_tpiu_swo.c index 6d1e94fa1..66fd7483b 100644 --- a/src/target/arm_tpiu_swo.c +++ b/src/target/arm_tpiu_swo.c @@ -887,7 +887,7 @@ static int arm_tpiu_swo_create(Jim_Interp *interp, struct arm_tpiu_swo_object *o COMMAND_REGISTRATION_DONE }; e = register_commands_with_data(cmd_ctx, NULL, obj_commands, obj); - if (ERROR_OK != e) + if (e != ERROR_OK) return JIM_ERR; list_add_tail(&obj->lh, &all_tpiu_swo); @@ -1037,7 +1037,7 @@ COMMAND_HANDLER(handle_tpiu_deprecated_config_command) } unsigned int cmd_idx = 0; - if (CMD_ARGC == cmd_idx) + if (cmd_idx == CMD_ARGC) return ERROR_COMMAND_SYNTAX_ERROR; if (!strcmp(CMD_ARGV[cmd_idx], "disable")) { @@ -1055,18 +1055,18 @@ COMMAND_HANDLER(handle_tpiu_deprecated_config_command) const char *pin_clk = NULL; if (!strcmp(CMD_ARGV[cmd_idx], "internal")) { cmd_idx++; - if (CMD_ARGC == cmd_idx) + if (cmd_idx == CMD_ARGC) return ERROR_COMMAND_SYNTAX_ERROR; output = CMD_ARGV[cmd_idx]; } else if (strcmp(CMD_ARGV[cmd_idx], "external")) return ERROR_COMMAND_SYNTAX_ERROR; cmd_idx++; - if (CMD_ARGC == cmd_idx) + if (cmd_idx == CMD_ARGC) return ERROR_COMMAND_SYNTAX_ERROR; if (!strcmp(CMD_ARGV[cmd_idx], "sync")) { protocol = CMD_ARGV[cmd_idx]; cmd_idx++; - if (CMD_ARGC == cmd_idx) + if (cmd_idx == CMD_ARGC) return ERROR_COMMAND_SYNTAX_ERROR; port_width = CMD_ARGV[cmd_idx]; } else { @@ -1074,20 +1074,20 @@ COMMAND_HANDLER(handle_tpiu_deprecated_config_command) return ERROR_COMMAND_SYNTAX_ERROR; protocol = CMD_ARGV[cmd_idx]; cmd_idx++; - if (CMD_ARGC == cmd_idx) + if (cmd_idx == CMD_ARGC) return ERROR_COMMAND_SYNTAX_ERROR; formatter = CMD_ARGV[cmd_idx]; } cmd_idx++; - if (CMD_ARGC == cmd_idx) + if (cmd_idx == CMD_ARGC) return ERROR_COMMAND_SYNTAX_ERROR; trace_clk = CMD_ARGV[cmd_idx]; cmd_idx++; - if (CMD_ARGC != cmd_idx) { + if (cmd_idx != CMD_ARGC) { pin_clk = CMD_ARGV[cmd_idx]; cmd_idx++; } - if (CMD_ARGC != cmd_idx) + if (cmd_idx != CMD_ARGC) return ERROR_COMMAND_SYNTAX_ERROR; LOG_INFO(MSG "Running: \'%s configure -protocol %s -traceclk %s" "%s%s" "%s%s" "%s%s" "%s%s\'", diff --git a/src/target/armv8.c b/src/target/armv8.c index 50010efbe..49e8b10b7 100644 --- a/src/target/armv8.c +++ b/src/target/armv8.c @@ -1823,7 +1823,7 @@ int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned /* Read register */ int retval = mem_ap_read_atomic_u32(armv8->debug_ap, armv8->debug_base + reg, &tmp); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* clear bitfield */ diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 6d13920f8..faed2d531 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -1138,7 +1138,7 @@ static int cortex_a_set_dscr_bits(struct target *target, /* Read DSCR */ int retval = mem_ap_read_atomic_u32(armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, &dscr); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; /* clear bitfield */ @@ -1197,7 +1197,7 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre /* Disable interrupts during single step if requested */ if (cortex_a->isrmasking_mode == CORTEX_A_ISRMASK_ON) { retval = cortex_a_set_dscr_bits(target, DSCR_INT_DIS, DSCR_INT_DIS); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; } @@ -1228,7 +1228,7 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre /* Re-enable interrupts if they were disabled */ if (cortex_a->isrmasking_mode == CORTEX_A_ISRMASK_ON) { retval = cortex_a_set_dscr_bits(target, DSCR_INT_DIS, 0); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; } diff --git a/src/target/etm.c b/src/target/etm.c index 6dc2bd48c..8555872ff 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -1418,7 +1418,7 @@ COMMAND_HANDLER(handle_etm_config_command) if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0) { int retval = register_commands(CMD_CTX, NULL, etm_capture_drivers[i]->commands); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { free(etm_ctx); return retval; } diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 249412a42..8fa43097c 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -1061,7 +1061,7 @@ static int mips_m4k_read_memory(struct target *target, target_addr_t address, /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */ /* endianness, but byte array should represent target endianness */ - if (ERROR_OK == retval) { + if (retval == ERROR_OK) { switch (size) { case 4: target_buffer_set_u32_array(target, buffer, count, t); @@ -1137,7 +1137,7 @@ static int mips_m4k_write_memory(struct target *target, target_addr_t address, free(t); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; return ERROR_OK; diff --git a/src/target/mips_mips64.c b/src/target/mips_mips64.c index 9ba46b753..56b0194e7 100644 --- a/src/target/mips_mips64.c +++ b/src/target/mips_mips64.c @@ -923,7 +923,7 @@ static int mips_mips64_read_memory(struct target *target, uint64_t address, retval = mips64_pracc_read_mem(ejtag_info, address, size, count, (void *)t); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("mips64_pracc_read_mem filed"); goto read_done; } diff --git a/src/target/nds32.c b/src/target/nds32.c index 372f82d0c..184f2fecc 100644 --- a/src/target/nds32.c +++ b/src/target/nds32.c @@ -330,16 +330,16 @@ static int nds32_set_core_reg(struct reg *reg, uint8_t *buf) reg->dirty = false; /* update registers to take effect right now */ - if (IR0 == mapped_regnum) { + if (mapped_regnum == IR0) { nds32_update_psw(nds32); - } else if (MR0 == mapped_regnum) { + } else if (mapped_regnum == MR0) { nds32_update_mmu_info(nds32); - } else if ((MR6 == mapped_regnum) || (MR7 == mapped_regnum)) { + } else if ((mapped_regnum == MR6) || (mapped_regnum == MR7)) { /* update lm information */ nds32_update_lm_info(nds32); - } else if (MR8 == mapped_regnum) { + } else if (mapped_regnum == MR8) { nds32_update_cache_info(nds32); - } else if (FUCPR == mapped_regnum) { + } else if (mapped_regnum == FUCPR) { /* update audio/fpu setting */ nds32_check_extension(nds32); } @@ -1951,7 +1951,7 @@ int nds32_examine_debug_reason(struct nds32 *nds32) nds32_step_without_watchpoint(nds32); /* before single_step, save exception address */ - if (ERROR_OK != result) + if (result != ERROR_OK) return ERROR_FAIL; target->debug_reason = DBG_REASON_WATCHPOINT; @@ -2059,7 +2059,7 @@ int nds32_halt(struct target *target) if (nds32_target_state(nds32, &state) != ERROR_OK) return ERROR_FAIL; - if (TARGET_HALTED != state) + if (state != TARGET_HALTED) /* TODO: if state == TARGET_HALTED, check ETYPE is DBGI or not */ if (ERROR_OK != aice_halt(aice)) return ERROR_FAIL; diff --git a/src/target/nds32_v2.c b/src/target/nds32_v2.c index 392bd6eb9..8916a59e0 100644 --- a/src/target/nds32_v2.c +++ b/src/target/nds32_v2.c @@ -37,35 +37,35 @@ static int nds32_v2_register_mapping(struct nds32 *nds32, int reg_no) uint32_t cur_level = nds32->current_interrupt_level; if ((1 <= cur_level) && (cur_level < max_level)) { - if (IR0 == reg_no) { + if (reg_no == IR0) { LOG_DEBUG("Map PSW to IPSW"); return IR1; - } else if (PC == reg_no) { + } else if (reg_no == PC) { LOG_DEBUG("Map PC to IPC"); return IR9; } } else if ((2 <= cur_level) && (cur_level < max_level)) { - if (R26 == reg_no) { + if (reg_no == R26) { LOG_DEBUG("Mapping P0 to P_P0"); return IR12; - } else if (R27 == reg_no) { + } else if (reg_no == R27) { LOG_DEBUG("Mapping P1 to P_P1"); return IR13; - } else if (IR1 == reg_no) { + } else if (reg_no == IR1) { LOG_DEBUG("Mapping IPSW to P_IPSW"); return IR2; - } else if (IR4 == reg_no) { + } else if (reg_no == IR4) { LOG_DEBUG("Mapping EVA to P_EVA"); return IR5; - } else if (IR6 == reg_no) { + } else if (reg_no == IR6) { LOG_DEBUG("Mapping ITYPE to P_ITYPE"); return IR7; - } else if (IR9 == reg_no) { + } else if (reg_no == IR9) { LOG_DEBUG("Mapping IPC to P_IPC"); return IR10; } } else if (cur_level == max_level) { - if (PC == reg_no) { + if (reg_no == PC) { LOG_DEBUG("Mapping PC to O_IPC"); return IR11; } @@ -436,7 +436,7 @@ static int nds32_v2_add_breakpoint(struct target *target, return ERROR_OK; } else if (breakpoint->type == BKPT_SOFT) { result = nds32_add_software_breakpoint(target, breakpoint); - if (ERROR_OK != result) { + if (result != ERROR_OK) { /* auto convert to hardware breakpoint if failed */ if (nds32->auto_convert_hw_bp) { /* convert to hardware breakpoint */ diff --git a/src/target/nds32_v3.c b/src/target/nds32_v3.c index f9cd47a40..fde86d6e8 100644 --- a/src/target/nds32_v3.c +++ b/src/target/nds32_v3.c @@ -310,7 +310,7 @@ static int nds32_v3_add_breakpoint(struct target *target, return ERROR_OK; } else if (breakpoint->type == BKPT_SOFT) { result = nds32_add_software_breakpoint(target, breakpoint); - if (ERROR_OK != result) { + if (result != ERROR_OK) { /* auto convert to hardware breakpoint if failed */ if (nds32->auto_convert_hw_bp) { /* convert to hardware breakpoint */ diff --git a/src/target/nds32_v3_common.c b/src/target/nds32_v3_common.c index 271ffdd1c..3abb3b9da 100644 --- a/src/target/nds32_v3_common.c +++ b/src/target/nds32_v3_common.c @@ -268,8 +268,8 @@ static int nds32_v3_get_exception_address(struct nds32 *nds32, nds32_get_mapped_reg(nds32, PC, &val_pc); - if ((NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE == reason) || - (NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE == reason)) { + if ((reason == NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE) || + (reason == NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE)) { if (edmsw & 0x4) /* check EDMSW.IS_16BIT */ val_pc -= 2; else @@ -320,7 +320,7 @@ static int nds32_v3_get_exception_address(struct nds32 *nds32, return ERROR_FAIL; } else if (match_count == 0) { /* global stop is precise exception */ - if ((NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP == reason) && nds32->global_stop) { + if ((reason == NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP) && nds32->global_stop) { /* parse instruction to get correct access address */ uint32_t val_pc; uint32_t opcode; @@ -553,7 +553,7 @@ int nds32_v3_write_buffer(struct target *target, target_addr_t address, int result; result = nds32_gdb_fileio_write_memory(nds32, address, size, buffer); - if (NDS_MEMORY_ACC_CPU == origin_access_channel) { + if (origin_access_channel == NDS_MEMORY_ACC_CPU) { memory->access_channel = NDS_MEMORY_ACC_CPU; aice_memory_access(aice, NDS_MEMORY_ACC_CPU); } diff --git a/src/target/nds32_v3m.c b/src/target/nds32_v3m.c index 952d0ebb4..ffd646f33 100644 --- a/src/target/nds32_v3m.c +++ b/src/target/nds32_v3m.c @@ -267,7 +267,7 @@ static int nds32_v3m_add_breakpoint(struct target *target, return ERROR_OK; } else if (breakpoint->type == BKPT_SOFT) { result = nds32_add_software_breakpoint(target, breakpoint); - if (ERROR_OK != result) { + if (result != ERROR_OK) { /* auto convert to hardware breakpoint if failed */ if (nds32->auto_convert_hw_bp) { /* convert to hardware breakpoint */ diff --git a/src/target/openrisc/jsp_server.c b/src/target/openrisc/jsp_server.c index 4dbe63527..e0a4475cf 100644 --- a/src/target/openrisc/jsp_server.c +++ b/src/target/openrisc/jsp_server.c @@ -103,7 +103,7 @@ static int jsp_new_connection(struct connection *connection) int retval = target_register_timer_callback(&jsp_poll_read, 1, TARGET_TIMER_TYPE_PERIODIC, jsp_service); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; return ERROR_OK; @@ -187,7 +187,7 @@ static int jsp_connection_closed(struct connection *connection) struct jsp_service *jsp_service = connection->service->priv; int retval = target_unregister_timer_callback(&jsp_poll_read, jsp_service); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; free(connection->priv); diff --git a/src/target/smp.c b/src/target/smp.c index 6501dc08a..94c4da5a8 100644 --- a/src/target/smp.c +++ b/src/target/smp.c @@ -141,7 +141,7 @@ COMMAND_HANDLER(handle_smp_gdb_command) if (CMD_ARGC == 1) { int coreid = 0; COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; target->gdb_service->core[1] = coreid; diff --git a/src/target/target.c b/src/target/target.c index 3772f8e3e..7dbcadba6 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -1546,7 +1546,7 @@ static int target_init_one(struct command_context *cmd_ctx, assert(type->init_target != NULL); int retval = type->init_target(cmd_ctx, target); - if (ERROR_OK != retval) { + if (retval != ERROR_OK) { LOG_ERROR("target '%s' init failed", target_name(target)); return retval; } @@ -1598,7 +1598,7 @@ static int target_init(struct command_context *cmd_ctx) for (target = all_targets; target; target = target->next) { retval = target_init_one(cmd_ctx, target); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; } @@ -1606,12 +1606,12 @@ static int target_init(struct command_context *cmd_ctx) return ERROR_OK; retval = target_register_user_commands(cmd_ctx); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = target_register_timer_callback(&handle_target, polling_interval, TARGET_TIMER_TYPE_PERIODIC, cmd_ctx->interp); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; return ERROR_OK; @@ -1632,15 +1632,15 @@ COMMAND_HANDLER(handle_target_init_command) target_initialized = true; retval = command_run_line(CMD_CTX, "init_targets"); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = command_run_line(CMD_CTX, "init_target_events"); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; retval = command_run_line(CMD_CTX, "init_board"); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; LOG_DEBUG("Initializing targets..."); @@ -3225,7 +3225,7 @@ COMMAND_HANDLER(handle_wait_halt_command) unsigned ms = DEFAULT_HALT_TIMEOUT; if (1 == CMD_ARGC) { int retval = parse_uint(CMD_ARGV[0], &ms); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return ERROR_COMMAND_SYNTAX_ERROR; } @@ -3281,13 +3281,13 @@ COMMAND_HANDLER(handle_halt_command) target->verbose_halt_msg = true; int retval = target_halt(target); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; if (CMD_ARGC == 1) { unsigned wait_local; retval = parse_uint(CMD_ARGV[0], &wait_local); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return ERROR_COMMAND_SYNTAX_ERROR; if (!wait_local) return ERROR_OK; @@ -3482,7 +3482,7 @@ COMMAND_HANDLER(handle_md_command) struct target *target = get_current_target(CMD_CTX); int retval = fn(target, address, size, count, buffer); - if (ERROR_OK == retval) + if (retval == ERROR_OK) target_handle_md_output(CMD, target, address, size, count, buffer); free(buffer); @@ -3639,7 +3639,7 @@ COMMAND_HANDLER(handle_load_image_command) int retval = CALL_COMMAND_HANDLER(parse_load_image_command_CMD_ARGV, &image, &min_address, &max_address); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; struct target *target = get_current_target(CMD_CTX); @@ -3700,7 +3700,7 @@ COMMAND_HANDLER(handle_load_image_command) free(buffer); } - if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) { + if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) { command_print(CMD, "downloaded %" PRIu32 " bytes " "in %fs (%0.3f KiB/s)", image_size, duration_elapsed(&bench), duration_kbps(&bench, image_size)); @@ -3757,7 +3757,7 @@ COMMAND_HANDLER(handle_dump_image_command) free(buffer); - if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) { + if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) { size_t filesize; retval = fileio_size(fileio, &filesize); if (retval != ERROR_OK) @@ -3902,7 +3902,7 @@ static COMMAND_HELPER(handle_verify_image_command_internal, enum verify_mode ver done: if (diffs > 0) retval = ERROR_FAIL; - if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) { + if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) { command_print(CMD, "verified %" PRIu32 " bytes " "in %fs (%0.3f KiB/s)", image_size, duration_elapsed(&bench), duration_kbps(&bench, image_size)); @@ -3972,7 +3972,7 @@ static int handle_bp_command_set(struct command_invocation *cmd, if (asid == 0) { retval = breakpoint_add(target, addr, length, hw); /* error is always logged in breakpoint_add(), do not print it again */ - if (ERROR_OK == retval) + if (retval == ERROR_OK) command_print(cmd, "breakpoint set at " TARGET_ADDR_FMT "", addr); } else if (addr == 0) { @@ -3982,7 +3982,7 @@ static int handle_bp_command_set(struct command_invocation *cmd, } retval = context_breakpoint_add(target, asid, length, hw); /* error is always logged in context_breakpoint_add(), do not print it again */ - if (ERROR_OK == retval) + if (retval == ERROR_OK) command_print(cmd, "Context breakpoint set at 0x%8.8" PRIx32 "", asid); } else { @@ -3992,7 +3992,7 @@ static int handle_bp_command_set(struct command_invocation *cmd, } retval = hybrid_breakpoint_add(target, addr, asid, length, hw); /* error is always logged in hybrid_breakpoint_add(), do not print it again */ - if (ERROR_OK == retval) + if (retval == ERROR_OK) command_print(cmd, "Hybrid breakpoint set at 0x%8.8" PRIx32 "", asid); } return retval; @@ -4123,7 +4123,7 @@ COMMAND_HANDLER(handle_wp_command) int retval = watchpoint_add(target, addr, length, type, data_value, data_mask); - if (ERROR_OK != retval) + if (retval != ERROR_OK) LOG_ERROR("Failure setting watchpoints"); return retval; @@ -5871,7 +5871,7 @@ static int target_create(struct jim_getopt_info *goi) /* create the target specific commands */ if (target->type->commands) { e = register_commands(cmd_ctx, NULL, target->type->commands); - if (ERROR_OK != e) + if (e != ERROR_OK) LOG_ERROR("unable to register '%s' commands", cp); } @@ -6101,7 +6101,7 @@ COMMAND_HANDLER(handle_fast_load_image_command) int retval = CALL_COMMAND_HANDLER(parse_load_image_command_CMD_ARGV, &image, &min_address, &max_address); - if (ERROR_OK != retval) + if (retval != ERROR_OK) return retval; struct duration bench; @@ -6173,7 +6173,7 @@ COMMAND_HANDLER(handle_fast_load_image_command) free(buffer); } - if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) { + if ((retval == ERROR_OK) && (duration_measure(&bench) == ERROR_OK)) { command_print(CMD, "Loaded %" PRIu32 " bytes " "in %fs (%0.3f KiB/s)", image_size, duration_elapsed(&bench), duration_kbps(&bench, image_size)); diff --git a/src/target/x86_32_common.c b/src/target/x86_32_common.c index b85e45119..d0b0e37e3 100644 --- a/src/target/x86_32_common.c +++ b/src/target/x86_32_common.c @@ -1428,7 +1428,7 @@ COMMAND_HANDLER(handle_iod_command) uint8_t *buffer = calloc(count, size); struct target *target = get_current_target(CMD_CTX); int retval = x86_32_common_read_io(target, address, size, buffer); - if (ERROR_OK == retval) + if (retval == ERROR_OK) handle_iod_output(CMD, target, address, size, count, buffer); free(buffer); return retval;