- convert spaces to tabs in at91sam7.[ch]
- add missing svn props git-svn-id: svn://svn.berlios.de/openocd/trunk@1009 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
ntfreak
parent
c90c48b00b
commit
279affdb98
1766
src/flash/at91sam7.c
1766
src/flash/at91sam7.c
File diff suppressed because it is too large
Load Diff
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@ -26,95 +26,94 @@
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#include "flash.h"
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#include "target.h"
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typedef struct at91sam7_flash_bank_s
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{
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/* chip id register */
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u32 cidr;
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u16 cidr_ext;
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u16 cidr_nvptyp;
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u16 cidr_arch;
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u16 cidr_sramsiz;
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u16 cidr_nvpsiz;
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u16 cidr_nvpsiz2;
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u16 cidr_eproc;
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u16 cidr_version;
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char *target_name;
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/* chip id register */
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u32 cidr;
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u16 cidr_ext;
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u16 cidr_nvptyp;
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u16 cidr_arch;
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u16 cidr_sramsiz;
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u16 cidr_nvpsiz;
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u16 cidr_nvpsiz2;
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u16 cidr_eproc;
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u16 cidr_version;
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char *target_name;
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/* flash auto-detection */
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u8 flash_autodetection;
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/* flash auto-detection */
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u8 flash_autodetection;
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/* flash geometry */
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u16 pages_per_sector;
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u16 pagesize;
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u16 pages_in_lockregion;
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/* flash geometry */
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u16 pages_per_sector;
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u16 pagesize;
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u16 pages_in_lockregion;
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/* nv memory bits */
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u16 num_lockbits_on;
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u16 lockbits;
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u16 num_nvmbits;
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u16 num_nvmbits_on;
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u16 nvmbits;
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u8 securitybit;
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/* nv memory bits */
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u16 num_lockbits_on;
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u16 lockbits;
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u16 num_nvmbits;
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u16 num_nvmbits_on;
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u16 nvmbits;
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u8 securitybit;
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/* 0: not init
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1: fmcn for nvbits (1uS)
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2: fmcn for flash (1.5uS) */
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u8 flashmode;
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/* 0: not init
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* 1: fmcn for nvbits (1uS)
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* 2: fmcn for flash (1.5uS) */
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u8 flashmode;
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/* main clock status */
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u8 mck_valid;
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u32 mck_freq;
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/* main clock status */
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u8 mck_valid;
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u32 mck_freq;
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/* external clock frequency */
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u32 ext_freq;
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/* external clock frequency */
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u32 ext_freq;
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} at91sam7_flash_bank_t;
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/* AT91SAM7 control registers */
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#define DBGU_CIDR 0xFFFFF240
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#define CKGR_MCFR 0xFFFFFC24
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#define CKGR_MOR 0xFFFFFC20
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#define CKGR_MCFR_MAINRDY 0x10000
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#define CKGR_PLLR 0xFFFFFC2c
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#define CKGR_PLLR_DIV 0xff
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#define CKGR_PLLR_MUL 0x07ff0000
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#define PMC_MCKR 0xFFFFFC30
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#define PMC_MCKR_CSS 0x03
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#define PMC_MCKR_PRES 0x1c
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#define DBGU_CIDR 0xFFFFF240
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#define CKGR_MCFR 0xFFFFFC24
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#define CKGR_MOR 0xFFFFFC20
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#define CKGR_MCFR_MAINRDY 0x10000
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#define CKGR_PLLR 0xFFFFFC2c
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#define CKGR_PLLR_DIV 0xff
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#define CKGR_PLLR_MUL 0x07ff0000
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#define PMC_MCKR 0xFFFFFC30
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#define PMC_MCKR_CSS 0x03
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#define PMC_MCKR_PRES 0x1c
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/* Flash Controller Commands */
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#define WP 0x01
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#define SLB 0x02
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#define WPL 0x03
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#define CLB 0x04
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#define EA 0x08
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#define SGPB 0x0B
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#define CGPB 0x0D
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#define SSB 0x0F
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#define WP 0x01
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#define SLB 0x02
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#define WPL 0x03
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#define CLB 0x04
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#define EA 0x08
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#define SGPB 0x0B
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#define CGPB 0x0D
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#define SSB 0x0F
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/* MC_FSR bit definitions */
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#define MC_FSR_FRDY 1
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#define MC_FSR_EOL 2
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#define MC_FSR_FRDY 1
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#define MC_FSR_EOL 2
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/* AT91SAM7 constants */
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#define RC_FREQ 32000
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#define RC_FREQ 32000
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/* Flash timing modes */
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#define FMR_TIMING_NONE 0
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#define FMR_TIMING_NVBITS 1
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#define FMR_TIMING_FLASH 2
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#define FMR_TIMING_NONE 0
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#define FMR_TIMING_NVBITS 1
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#define FMR_TIMING_FLASH 2
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/* Flash size constants */
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#define FLASH_SIZE_8KB 1
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#define FLASH_SIZE_16KB 2
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#define FLASH_SIZE_32KB 3
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#define FLASH_SIZE_64KB 5
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#define FLASH_SIZE_128KB 7
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#define FLASH_SIZE_256KB 9
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#define FLASH_SIZE_512KB 10
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#define FLASH_SIZE_1024KB 12
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#define FLASH_SIZE_2048KB 14
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#define FLASH_SIZE_8KB 1
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#define FLASH_SIZE_16KB 2
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#define FLASH_SIZE_32KB 3
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#define FLASH_SIZE_64KB 5
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#define FLASH_SIZE_128KB 7
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#define FLASH_SIZE_256KB 9
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#define FLASH_SIZE_512KB 10
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#define FLASH_SIZE_1024KB 12
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#define FLASH_SIZE_2048KB 14
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#endif /* AT91SAM7_H */
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@ -80,25 +80,23 @@ extern flash_driver_t lpc288x_flash;
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extern flash_driver_t ocl_flash;
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flash_driver_t *flash_drivers[] = {
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&lpc2000_flash,
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&cfi_flash,
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&at91sam7_flash,
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&at91sam7_old_flash,
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&str7x_flash,
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&str9x_flash,
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&aduc702x_flash,
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&stellaris_flash,
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&str9xpec_flash,
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&stm32x_flash,
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&tms470_flash,
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&ecosflash_flash,
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&lpc288x_flash,
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&ocl_flash,
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NULL,
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&lpc2000_flash,
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&cfi_flash,
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&at91sam7_flash,
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&at91sam7_old_flash,
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&str7x_flash,
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&str9x_flash,
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&aduc702x_flash,
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&stellaris_flash,
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&str9xpec_flash,
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&stm32x_flash,
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&tms470_flash,
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&ecosflash_flash,
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&lpc288x_flash,
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&ocl_flash,
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NULL,
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};
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flash_bank_t *flash_banks;
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static command_t *flash_cmd;
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@ -92,13 +92,13 @@ extern flash_bank_t *get_flash_bank_by_num(int num);
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extern flash_bank_t *get_flash_bank_by_num_noprobe(int num);
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extern flash_bank_t *get_flash_bank_by_addr(target_t *target, u32 addr);
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#define ERROR_FLASH_BANK_INVALID (-900)
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#define ERROR_FLASH_SECTOR_INVALID (-901)
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#define ERROR_FLASH_OPERATION_FAILED (-902)
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#define ERROR_FLASH_DST_OUT_OF_BANK (-903)
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#define ERROR_FLASH_DST_BREAKS_ALIGNMENT (-904)
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#define ERROR_FLASH_BUSY (-905)
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#define ERROR_FLASH_SECTOR_NOT_ERASED (-906)
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#define ERROR_FLASH_BANK_NOT_PROBED (-907)
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#define ERROR_FLASH_BANK_INVALID (-900)
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#define ERROR_FLASH_SECTOR_INVALID (-901)
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#define ERROR_FLASH_OPERATION_FAILED (-902)
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#define ERROR_FLASH_DST_OUT_OF_BANK (-903)
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#define ERROR_FLASH_DST_BREAKS_ALIGNMENT (-904)
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#define ERROR_FLASH_BUSY (-905)
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#define ERROR_FLASH_SECTOR_NOT_ERASED (-906)
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#define ERROR_FLASH_BANK_NOT_PROBED (-907)
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#endif /* FLASH_H */
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@ -107,13 +107,13 @@ int cortex_m3_clear_halt(target_t *target)
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cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
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swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
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/* Read Debug Fault Status Register */
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ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
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/* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */
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ahbap_write_system_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
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LOG_DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr);
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/* Read Debug Fault Status Register */
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ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
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/* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */
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ahbap_write_system_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
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LOG_DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr);
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return ERROR_OK;
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return ERROR_OK;
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}
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int cortex_m3_single_step_core(target_t *target)
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@ -287,8 +287,8 @@ int cortex_m3_examine_exception_reason(target_t *target)
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break;
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}
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swjdp_transaction_endcheck(swjdp);
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LOG_DEBUG("%s SHCSR 0x%x, SR 0x%x, CFSR 0x%x, AR 0x%x", armv7m_exception_string(armv7m->exception_number), \
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shcsr, except_sr, cfsr, except_ar);
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LOG_DEBUG("%s SHCSR 0x%x, SR 0x%x, CFSR 0x%x, AR 0x%x", armv7m_exception_string(armv7m->exception_number), \
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shcsr, except_sr, cfsr, except_ar);
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return ERROR_OK;
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}
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@ -363,9 +363,9 @@ int cortex_m3_debug_entry(target_t *target)
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}
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LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s",
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armv7m_mode_strings[armv7m->core_mode],
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*(u32*)(armv7m->core_cache->reg_list[15].value),
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Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
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armv7m_mode_strings[armv7m->core_mode],
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*(u32*)(armv7m->core_cache->reg_list[15].value),
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Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
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if (armv7m->post_debug_entry)
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armv7m->post_debug_entry(target);
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@ -439,7 +439,7 @@ int cortex_m3_poll(target_t *target)
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*/
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#if 0
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/* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */
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/* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */
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ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
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LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name( nvp_target_state, target->state )->name );
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#endif
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@ -455,7 +455,7 @@ int cortex_m3_halt(target_t *target)
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swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
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LOG_DEBUG("target->state: %s",
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Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
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Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
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if (target->state == TARGET_HALTED)
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{
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@ -518,7 +518,7 @@ int cortex_m3_soft_reset_halt(struct target_s *target)
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retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
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if (retval == ERROR_OK)
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{
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ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
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ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
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if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
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{
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LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x", dcb_dhcsr, cortex_m3->nvic_dfsr);
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@ -563,11 +563,9 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
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if (debug_execution)
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{
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/* Disable interrupts */
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/*
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We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
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This is probably the same inssue as Cortex-M3 Errata 377493:
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C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken.
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*/
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/* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
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* This is probably the same inssue as Cortex-M3 Errata 377493:
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* C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */
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buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
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/* Make sure we are in Thumb mode */
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buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
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@ -683,7 +681,7 @@ int cortex_m3_assert_reset(target_t *target)
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int assert_srst = 1;
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LOG_DEBUG("target->state: %s",
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Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
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Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
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if (!(jtag_reset_config & RESET_HAS_SRST))
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{
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@ -765,10 +763,10 @@ int cortex_m3_assert_reset(target_t *target)
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{
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/* I do not know why this is necessary, but it fixes strange effects
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(step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */
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* (step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */
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u32 tmp;
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ahbap_read_system_atomic_u32(swjdp, NVIC_AIRCR, &tmp );
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}
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}
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}
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target->state = TARGET_RESET;
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@ -776,12 +774,12 @@ int cortex_m3_assert_reset(target_t *target)
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armv7m_invalidate_core_regs(target);
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if (target->reset_halt)
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{
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int retval;
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if (target->reset_halt)
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{
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int retval;
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if ((retval = target_halt(target))!=ERROR_OK)
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return retval;
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}
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}
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return ERROR_OK;
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}
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@ -789,7 +787,7 @@ int cortex_m3_assert_reset(target_t *target)
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int cortex_m3_deassert_reset(target_t *target)
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{
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LOG_DEBUG("target->state: %s",
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Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
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Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
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/* deassert reset lines */
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jtag_add_reset(0, 0);
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