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- convert spaces to tabs in at91sam7.[ch] 

- add missing svn props

git-svn-id: svn://svn.berlios.de/openocd/trunk@1009 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
ntfreak 2008-09-27 13:00:01 +00:00
parent c90c48b00b
commit 279affdb98
10 changed files with 5400 additions and 5411 deletions
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1766
src/flash/at91sam7.c
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File diff suppressed because it is too large Load Diff

133
src/flash/at91sam7.h
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@ -26,95 +26,94 @@
#include "flash.h" #include "flash.h"
#include "target.h" #include "target.h"
typedef struct at91sam7_flash_bank_s typedef struct at91sam7_flash_bank_s
{ {
/* chip id register */ /* chip id register */
u32 cidr; u32 cidr;
u16 cidr_ext; u16 cidr_ext;
u16 cidr_nvptyp; u16 cidr_nvptyp;
u16 cidr_arch; u16 cidr_arch;
u16 cidr_sramsiz; u16 cidr_sramsiz;
u16 cidr_nvpsiz; u16 cidr_nvpsiz;
u16 cidr_nvpsiz2; u16 cidr_nvpsiz2;
u16 cidr_eproc; u16 cidr_eproc;
u16 cidr_version; u16 cidr_version;
char *target_name; char *target_name;
/* flash auto-detection */ /* flash auto-detection */
u8 flash_autodetection; u8 flash_autodetection;
/* flash geometry */ /* flash geometry */
u16 pages_per_sector; u16 pages_per_sector;
u16 pagesize; u16 pagesize;
u16 pages_in_lockregion; u16 pages_in_lockregion;
/* nv memory bits */ /* nv memory bits */
u16 num_lockbits_on; u16 num_lockbits_on;
u16 lockbits; u16 lockbits;
u16 num_nvmbits; u16 num_nvmbits;
u16 num_nvmbits_on; u16 num_nvmbits_on;
u16 nvmbits; u16 nvmbits;
u8 securitybit; u8 securitybit;
/* 0: not init /* 0: not init
1: fmcn for nvbits (1uS) * 1: fmcn for nvbits (1uS)
2: fmcn for flash (1.5uS) */ * 2: fmcn for flash (1.5uS) */
u8 flashmode; u8 flashmode;
/* main clock status */ /* main clock status */
u8 mck_valid; u8 mck_valid;
u32 mck_freq; u32 mck_freq;
/* external clock frequency */ /* external clock frequency */
u32 ext_freq; u32 ext_freq;
} at91sam7_flash_bank_t; } at91sam7_flash_bank_t;
/* AT91SAM7 control registers */ /* AT91SAM7 control registers */
#define DBGU_CIDR 0xFFFFF240 #define DBGU_CIDR 0xFFFFF240
#define CKGR_MCFR 0xFFFFFC24 #define CKGR_MCFR 0xFFFFFC24
#define CKGR_MOR 0xFFFFFC20 #define CKGR_MOR 0xFFFFFC20
#define CKGR_MCFR_MAINRDY 0x10000 #define CKGR_MCFR_MAINRDY 0x10000
#define CKGR_PLLR 0xFFFFFC2c #define CKGR_PLLR 0xFFFFFC2c
#define CKGR_PLLR_DIV 0xff #define CKGR_PLLR_DIV 0xff
#define CKGR_PLLR_MUL 0x07ff0000 #define CKGR_PLLR_MUL 0x07ff0000
#define PMC_MCKR 0xFFFFFC30 #define PMC_MCKR 0xFFFFFC30
#define PMC_MCKR_CSS 0x03 #define PMC_MCKR_CSS 0x03
#define PMC_MCKR_PRES 0x1c #define PMC_MCKR_PRES 0x1c
/* Flash Controller Commands */ /* Flash Controller Commands */
#define WP 0x01 #define WP 0x01
#define SLB 0x02 #define SLB 0x02
#define WPL 0x03 #define WPL 0x03
#define CLB 0x04 #define CLB 0x04
#define EA 0x08 #define EA 0x08
#define SGPB 0x0B #define SGPB 0x0B
#define CGPB 0x0D #define CGPB 0x0D
#define SSB 0x0F #define SSB 0x0F
/* MC_FSR bit definitions */ /* MC_FSR bit definitions */
#define MC_FSR_FRDY 1 #define MC_FSR_FRDY 1
#define MC_FSR_EOL 2 #define MC_FSR_EOL 2
/* AT91SAM7 constants */ /* AT91SAM7 constants */
#define RC_FREQ 32000 #define RC_FREQ 32000
/* Flash timing modes */ /* Flash timing modes */
#define FMR_TIMING_NONE 0 #define FMR_TIMING_NONE 0
#define FMR_TIMING_NVBITS 1 #define FMR_TIMING_NVBITS 1
#define FMR_TIMING_FLASH 2 #define FMR_TIMING_FLASH 2
/* Flash size constants */ /* Flash size constants */
#define FLASH_SIZE_8KB 1 #define FLASH_SIZE_8KB 1
#define FLASH_SIZE_16KB 2 #define FLASH_SIZE_16KB 2
#define FLASH_SIZE_32KB 3 #define FLASH_SIZE_32KB 3
#define FLASH_SIZE_64KB 5 #define FLASH_SIZE_64KB 5
#define FLASH_SIZE_128KB 7 #define FLASH_SIZE_128KB 7
#define FLASH_SIZE_256KB 9 #define FLASH_SIZE_256KB 9
#define FLASH_SIZE_512KB 10 #define FLASH_SIZE_512KB 10
#define FLASH_SIZE_1024KB 12 #define FLASH_SIZE_1024KB 12
#define FLASH_SIZE_2048KB 14 #define FLASH_SIZE_2048KB 14
#endif /* AT91SAM7_H */ #endif /* AT91SAM7_H */

32
src/flash/flash.c
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@ -80,25 +80,23 @@ extern flash_driver_t lpc288x_flash;
extern flash_driver_t ocl_flash; extern flash_driver_t ocl_flash;
flash_driver_t *flash_drivers[] = { flash_driver_t *flash_drivers[] = {
&lpc2000_flash, &lpc2000_flash,
&cfi_flash, &cfi_flash,
&at91sam7_flash, &at91sam7_flash,
&at91sam7_old_flash, &at91sam7_old_flash,
&str7x_flash, &str7x_flash,
&str9x_flash, &str9x_flash,
&aduc702x_flash, &aduc702x_flash,
&stellaris_flash, &stellaris_flash,
&str9xpec_flash, &str9xpec_flash,
&stm32x_flash, &stm32x_flash,
&tms470_flash, &tms470_flash,
&ecosflash_flash, &ecosflash_flash,
&lpc288x_flash, &lpc288x_flash,
&ocl_flash, &ocl_flash,
NULL, NULL,
}; };
flash_bank_t *flash_banks; flash_bank_t *flash_banks;
static command_t *flash_cmd; static command_t *flash_cmd;

16
src/flash/flash.h
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@ -92,13 +92,13 @@ extern flash_bank_t *get_flash_bank_by_num(int num);
extern flash_bank_t *get_flash_bank_by_num_noprobe(int num); extern flash_bank_t *get_flash_bank_by_num_noprobe(int num);
extern flash_bank_t *get_flash_bank_by_addr(target_t *target, u32 addr); extern flash_bank_t *get_flash_bank_by_addr(target_t *target, u32 addr);
#define ERROR_FLASH_BANK_INVALID (-900) #define ERROR_FLASH_BANK_INVALID (-900)
#define ERROR_FLASH_SECTOR_INVALID (-901) #define ERROR_FLASH_SECTOR_INVALID (-901)
#define ERROR_FLASH_OPERATION_FAILED (-902) #define ERROR_FLASH_OPERATION_FAILED (-902)
#define ERROR_FLASH_DST_OUT_OF_BANK (-903) #define ERROR_FLASH_DST_OUT_OF_BANK (-903)
#define ERROR_FLASH_DST_BREAKS_ALIGNMENT (-904) #define ERROR_FLASH_DST_BREAKS_ALIGNMENT (-904)
#define ERROR_FLASH_BUSY (-905) #define ERROR_FLASH_BUSY (-905)
#define ERROR_FLASH_SECTOR_NOT_ERASED (-906) #define ERROR_FLASH_SECTOR_NOT_ERASED (-906)
#define ERROR_FLASH_BANK_NOT_PROBED (-907) #define ERROR_FLASH_BANK_NOT_PROBED (-907)
#endif /* FLASH_H */ #endif /* FLASH_H */

52
src/target/cortex_m3.c
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@ -107,13 +107,13 @@ int cortex_m3_clear_halt(target_t *target)
cortex_m3_common_t *cortex_m3 = armv7m->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &cortex_m3->swjdp_info; swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
/* Read Debug Fault Status Register */ /* Read Debug Fault Status Register */
ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
/* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */ /* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */
ahbap_write_system_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr); ahbap_write_system_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
LOG_DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr); LOG_DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr);
return ERROR_OK; return ERROR_OK;
} }
int cortex_m3_single_step_core(target_t *target) int cortex_m3_single_step_core(target_t *target)
@ -287,8 +287,8 @@ int cortex_m3_examine_exception_reason(target_t *target)
break; break;
} }
swjdp_transaction_endcheck(swjdp); swjdp_transaction_endcheck(swjdp);
LOG_DEBUG("%s SHCSR 0x%x, SR 0x%x, CFSR 0x%x, AR 0x%x", armv7m_exception_string(armv7m->exception_number), \ LOG_DEBUG("%s SHCSR 0x%x, SR 0x%x, CFSR 0x%x, AR 0x%x", armv7m_exception_string(armv7m->exception_number), \
shcsr, except_sr, cfsr, except_ar); shcsr, except_sr, cfsr, except_ar);
return ERROR_OK; return ERROR_OK;
} }
@ -363,9 +363,9 @@ int cortex_m3_debug_entry(target_t *target)
} }
LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s", LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s",
armv7m_mode_strings[armv7m->core_mode], armv7m_mode_strings[armv7m->core_mode],
*(u32*)(armv7m->core_cache->reg_list[15].value), *(u32*)(armv7m->core_cache->reg_list[15].value),
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
if (armv7m->post_debug_entry) if (armv7m->post_debug_entry)
armv7m->post_debug_entry(target); armv7m->post_debug_entry(target);
@ -439,7 +439,7 @@ int cortex_m3_poll(target_t *target)
*/ */
#if 0 #if 0
/* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */ /* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */
ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name( nvp_target_state, target->state )->name ); LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name( nvp_target_state, target->state )->name );
#endif #endif
@ -455,7 +455,7 @@ int cortex_m3_halt(target_t *target)
swjdp_common_t *swjdp = &cortex_m3->swjdp_info; swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
LOG_DEBUG("target->state: %s", LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name ); Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
if (target->state == TARGET_HALTED) if (target->state == TARGET_HALTED)
{ {
@ -518,7 +518,7 @@ int cortex_m3_soft_reset_halt(struct target_s *target)
retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
if (retval == ERROR_OK) if (retval == ERROR_OK)
{ {
ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH)) if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
{ {
LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x", dcb_dhcsr, cortex_m3->nvic_dfsr); LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x", dcb_dhcsr, cortex_m3->nvic_dfsr);
@ -563,11 +563,9 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
if (debug_execution) if (debug_execution)
{ {
/* Disable interrupts */ /* Disable interrupts */
/* /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS, * This is probably the same inssue as Cortex-M3 Errata 377493:
This is probably the same inssue as Cortex-M3 Errata 377493: * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */
C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken.
*/
buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1); buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
/* Make sure we are in Thumb mode */ /* Make sure we are in Thumb mode */
buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32, buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
@ -683,7 +681,7 @@ int cortex_m3_assert_reset(target_t *target)
int assert_srst = 1; int assert_srst = 1;
LOG_DEBUG("target->state: %s", LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name ); Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
if (!(jtag_reset_config & RESET_HAS_SRST)) if (!(jtag_reset_config & RESET_HAS_SRST))
{ {
@ -765,10 +763,10 @@ int cortex_m3_assert_reset(target_t *target)
{ {
/* I do not know why this is necessary, but it fixes strange effects /* I do not know why this is necessary, but it fixes strange effects
(step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */ * (step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */
u32 tmp; u32 tmp;
ahbap_read_system_atomic_u32(swjdp, NVIC_AIRCR, &tmp ); ahbap_read_system_atomic_u32(swjdp, NVIC_AIRCR, &tmp );
} }
} }
target->state = TARGET_RESET; target->state = TARGET_RESET;
@ -776,12 +774,12 @@ int cortex_m3_assert_reset(target_t *target)
armv7m_invalidate_core_regs(target); armv7m_invalidate_core_regs(target);
if (target->reset_halt) if (target->reset_halt)
{ {
int retval; int retval;
if ((retval = target_halt(target))!=ERROR_OK) if ((retval = target_halt(target))!=ERROR_OK)
return retval; return retval;
} }
return ERROR_OK; return ERROR_OK;
} }
@ -789,7 +787,7 @@ int cortex_m3_assert_reset(target_t *target)
int cortex_m3_deassert_reset(target_t *target) int cortex_m3_deassert_reset(target_t *target)
{ {
LOG_DEBUG("target->state: %s", LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
/* deassert reset lines */ /* deassert reset lines */
jtag_add_reset(0, 0); jtag_add_reset(0, 0);