interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

flash/nor/stm32l4x: add support of STM32L4P5/L4Q5x devices 

STM32L4P/Q devices have:
 - similar flash layout as STM32L4R/S devices
 - 1024K of flash memory (some parts have 512K only)

tested on NUCLEO-L4P5ZG using board/st_nucleo_l4.cfg

Change-Id: I77047351bc7dcd7c76d0f31a77be73005104a06f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5392
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Tarek BOCHKATI 2020-01-06 18:33:42 +01:00 committed by Tomas Vanek
parent a6a642bf72
commit 251eb035fc
1 changed files with 29 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
src/flash/nor/stm32l4x.c
View File

@ -51,12 +51,17 @@
* RM0394 devices have a single bank only.
*
* RM0432 devices have single and dual bank operating modes.
* The FLASH size is 1Mbyte or 2Mbyte.
* - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
* - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
* Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
*
* Bank mode is controlled by two different bits in option bytes register.
* In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
* In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
* - for STM32L4R/Sxx
* In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
* In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
* - for STM32L4P5/Q5x
* In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
* In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
*
*/
@ -169,6 +174,10 @@ static const struct stm32l4_rev stm32_470_revs[] = {
{ 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
};
static const struct stm32l4_rev stm32_471_revs[] = {
{ 0x1000, "1" },
};
static const struct stm32l4_rev stm32_495_revs[] = {
{ 0x2001, "2.1" },
};
@ -234,6 +243,16 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.flash_regs_base = 0x40022000,
.fsize_addr = 0x1FFF75E0,
},
{
.id = 0x471,
.revs = stm32_471_revs,
.num_revs = ARRAY_SIZE(stm32_471_revs),
.device_str = "STM32L4P5/L4Q5x",
.max_flash_size_kb = 1024,
.has_dual_bank = true,
.flash_regs_base = 0x40022000,
.fsize_addr = 0x1FFF75E0,
},
{
.id = 0x495,
.revs = stm32_495_revs,
@ -801,17 +820,22 @@ static int stm32l4_probe(struct flash_bank *bank)
stm32l4_info->bank1_sectors = num_pages;
break;
case 0x470:
case 0x471:
/* STM32L4R/S can be single/dual bank:
* if size = 2M check DBANK bit(22)
* if size = 1M check DB1M bit(21)
* STM32L4P/Q can be single/dual bank
* if size = 1M check DBANK bit(22)
* if size = 512K check DB512K bit(21)
* in single bank configuration the page size is 8K
* else (dual bank) the page size is 4K without gap between banks
*/
page_size = 8192;
num_pages = flash_size_in_kb / 8;
stm32l4_info->bank1_sectors = num_pages;
if ((flash_size_in_kb == 2048 && (options & BIT(22))) ||
(flash_size_in_kb == 1024 && (options & BIT(21)))) {
const bool use_dbank_bit = flash_size_in_kb == part_info->max_flash_size_kb;
if ((use_dbank_bit && (options & BIT(22))) ||
(!use_dbank_bit && (options & BIT(21)))) {
stm32l4_info->dual_bank_mode = true;
page_size = 4096;
num_pages = flash_size_in_kb / 4;