flash/nor/at91sam4: remove FWS=6, rename at91samg to atsamg
FWS=6 workaround removed, as this appears to be a copy-paste error from the SAM3X family. Originally addressed in http://openocd.zylin.com/3837 but not all occurences were removed. Atmel changed chip naming and removed 91 prefix for atsamg, samd... Change-Id: Ia2b43da82b2ff9b1c85fdb456a0a198ab095243d Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3926 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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@ -464,7 +464,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 1024 * 1024,
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.nsectors = 128,
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@ -499,7 +499,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 512 * 1024,
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.nsectors = 64,
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@ -532,7 +532,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 512 * 1024,
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.nsectors = 64,
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@ -565,7 +565,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 512 * 1024,
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.nsectors = 64,
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@ -598,7 +598,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 1024 * 1024,
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.nsectors = 128,
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@ -631,7 +631,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 1024 * 1024,
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.nsectors = 128,
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@ -1279,7 +1279,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK0_BASE_SD,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 512 * 1024,
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.nsectors = 64,
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@ -1295,7 +1295,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 1,
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.base_address = FLASH_BANK1_BASE_1024K_SD,
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.controller_address = 0x400e0c00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 512 * 1024,
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.nsectors = 64,
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@ -1305,10 +1305,10 @@ static const struct sam4_chip_details all_sam4_details[] = {
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},
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},
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/* at91samg53n19 */
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/* atsamg53n19 */
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{
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.chipid_cidr = 0x247e0ae0,
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.name = "at91samg53n19",
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.name = "atsamg53n19",
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.total_flash_size = 512 * 1024,
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.total_sram_size = 96 * 1024,
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.n_gpnvms = 2,
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@ -1323,7 +1323,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 512 * 1024,
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.nsectors = 64,
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