jtag/vdebug: adding xtensa config
This change adds the extensa sample target and board configurations. it removes the obsoleted vd_xtensa_jtag.cfg from targets. Change-Id: I9d4d25abde46c0b15e5211a973012447872cb405 Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7723 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Cadence virtual debug interface
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# Xtensa xt8 through JTAG
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source [find interface/vdebug.cfg]
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set CHIPNAME xt8
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set CPUTAPID 0x120034e5
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# vdebug select transport
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transport select jtag
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# JTAG reset config, frequency and reset delay
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reset_config trst_and_srst
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adapter speed 50000
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adapter srst delay 5
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# BFM hierarchical path and input clk period
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vdebug bfm_path Testbench.u_vd_jtag_bfm 10ns
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# DMA Memories to access backdoor, the values come from generated xtensa-core-xt8.cfg
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#vdebug mem_path Testbench.Xtsubsystem.Core0.iram0.iram0.mem.dataArray 0x40000000 0x100000
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#vdebug mem_path Testbench.Xtsubsystem.Core0.dram0.dram0.mem.dataArray 0x3ff00000 0x40000
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# Create Xtensa target first
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source [find target/xtensa.cfg]
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# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
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source [find target/xtensa-core-xt8.cfg]
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Cadence virtual debug interface
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# for Palladium emulation systems
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#
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# TODO: Enable backdoor memory access
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# set _MEMSTART 0x00000000
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# set _MEMSIZE 0x100000
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# BFM hierarchical path and input clk period
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vdebug bfm_path dut_top.JTAG 10ns
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# DMA Memories to access backdoor (up to 4)
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# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
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# Create Xtensa target first
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source [find target/xtensa.cfg]
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# Configure Xtensa core parameters next
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# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
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# register target
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proc vdebug_examine_end {} {
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# vdebug register_target
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}
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# Default hooks
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$_TARGETNAME configure -event examine-end { vdebug_examine_end }
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# SPDX-License-Identifier: GPL-2.0-or-later
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# OpenOCD configuration file for Xtensa xt8 target
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# Core definition and ABI
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xtensa xtdef LX
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xtensa xtopt arnum 32
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xtensa xtopt windowed 1
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# Exception/Interrupt Options
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xtensa xtopt exceptions 1
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xtensa xtopt hipriints 1
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xtensa xtopt intlevels 3
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xtensa xtopt excmlevel 1
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# Cache Options
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xtensa xtmem icache 16 1024 1
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xtensa xtmem dcache 16 1024 1 1
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# Memory Options
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xtensa xtmem iram 0x40000000 1048576
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xtensa xtmem dram 0x3ff00000 262144
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xtensa xtmem srom 0x50000000 131072
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xtensa xtmem sram 0x60000000 4194304
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# Memory Protection/Translation Options
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# Debug Options
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xtensa xtopt debuglevel 3
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xtensa xtopt ibreaknum 2
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xtensa xtopt dbreaknum 2
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# Core Registers
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xtensa xtregs 127
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xtensa xtreg a0 0x0000
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xtensa xtreg a1 0x0001
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xtensa xtreg a2 0x0002
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xtensa xtreg a3 0x0003
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xtensa xtreg a4 0x0004
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xtensa xtreg a5 0x0005
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xtensa xtreg a6 0x0006
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xtensa xtreg a7 0x0007
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xtensa xtreg a8 0x0008
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xtensa xtreg a9 0x0009
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xtensa xtreg a10 0x000a
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xtensa xtreg a11 0x000b
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xtensa xtreg a12 0x000c
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xtensa xtreg a13 0x000d
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xtensa xtreg a14 0x000e
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xtensa xtreg a15 0x000f
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xtensa xtreg pc 0x0020
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xtensa xtreg ar0 0x0100
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xtensa xtreg ar1 0x0101
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xtensa xtreg ar2 0x0102
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xtensa xtreg ar3 0x0103
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xtensa xtreg ar4 0x0104
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xtensa xtreg ar5 0x0105
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xtensa xtreg ar6 0x0106
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xtensa xtreg ar7 0x0107
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xtensa xtreg ar8 0x0108
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xtensa xtreg ar9 0x0109
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xtensa xtreg ar10 0x010a
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xtensa xtreg ar11 0x010b
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xtensa xtreg ar12 0x010c
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xtensa xtreg ar13 0x010d
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xtensa xtreg ar14 0x010e
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xtensa xtreg ar15 0x010f
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xtensa xtreg ar16 0x0110
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xtensa xtreg ar17 0x0111
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xtensa xtreg ar18 0x0112
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xtensa xtreg ar19 0x0113
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xtensa xtreg ar20 0x0114
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xtensa xtreg ar21 0x0115
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xtensa xtreg ar22 0x0116
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xtensa xtreg ar23 0x0117
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xtensa xtreg ar24 0x0118
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xtensa xtreg ar25 0x0119
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xtensa xtreg ar26 0x011a
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xtensa xtreg ar27 0x011b
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xtensa xtreg ar28 0x011c
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xtensa xtreg ar29 0x011d
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xtensa xtreg ar30 0x011e
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xtensa xtreg ar31 0x011f
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xtensa xtreg lbeg 0x0200
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xtensa xtreg lend 0x0201
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xtensa xtreg lcount 0x0202
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xtensa xtreg sar 0x0203
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xtensa xtreg windowbase 0x0248
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xtensa xtreg windowstart 0x0249
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xtensa xtreg configid0 0x02b0
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xtensa xtreg configid1 0x02d0
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xtensa xtreg ps 0x02e6
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xtensa xtreg expstate 0x03e6
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xtensa xtreg mmid 0x0259
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xtensa xtreg ibreakenable 0x0260
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xtensa xtreg ddr 0x0268
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xtensa xtreg ibreaka0 0x0280
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xtensa xtreg ibreaka1 0x0281
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xtensa xtreg dbreaka0 0x0290
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xtensa xtreg dbreaka1 0x0291
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xtensa xtreg dbreakc0 0x02a0
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xtensa xtreg dbreakc1 0x02a1
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xtensa xtreg epc1 0x02b1
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xtensa xtreg epc2 0x02b2
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xtensa xtreg epc3 0x02b3
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xtensa xtreg depc 0x02c0
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xtensa xtreg eps2 0x02c2
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xtensa xtreg eps3 0x02c3
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xtensa xtreg excsave1 0x02d1
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xtensa xtreg excsave2 0x02d2
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xtensa xtreg excsave3 0x02d3
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xtensa xtreg interrupt 0x02e2
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xtensa xtreg intset 0x02e2
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xtensa xtreg intclear 0x02e3
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xtensa xtreg intenable 0x02e4
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xtensa xtreg exccause 0x02e8
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xtensa xtreg debugcause 0x02e9
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xtensa xtreg ccount 0x02ea
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xtensa xtreg icount 0x02ec
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xtensa xtreg icountlevel 0x02ed
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xtensa xtreg excvaddr 0x02ee
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xtensa xtreg ccompare0 0x02f0
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xtensa xtreg ccompare1 0x02f1
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xtensa xtreg pwrctl 0x200f
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xtensa xtreg pwrstat 0x2010
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xtensa xtreg eristat 0x2011
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xtensa xtreg cs_itctrl 0x2012
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xtensa xtreg cs_claimset 0x2013
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xtensa xtreg cs_claimclr 0x2014
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xtensa xtreg cs_lockaccess 0x2015
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xtensa xtreg cs_lockstatus 0x2016
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xtensa xtreg cs_authstatus 0x2017
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xtensa xtreg fault_info 0x2026
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xtensa xtreg trax_id 0x2027
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xtensa xtreg trax_control 0x2028
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xtensa xtreg trax_status 0x2029
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xtensa xtreg trax_data 0x202a
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xtensa xtreg trax_address 0x202b
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xtensa xtreg trax_pctrigger 0x202c
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xtensa xtreg trax_pcmatch 0x202d
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xtensa xtreg trax_delay 0x202e
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xtensa xtreg trax_memstart 0x202f
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xtensa xtreg trax_memend 0x2030
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xtensa xtreg pmg 0x203e
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xtensa xtreg pmpc 0x203f
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xtensa xtreg pm0 0x2040
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xtensa xtreg pm1 0x2041
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xtensa xtreg pmctrl0 0x2042
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xtensa xtreg pmctrl1 0x2043
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xtensa xtreg pmstat0 0x2044
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xtensa xtreg pmstat1 0x2045
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xtensa xtreg ocdid 0x2046
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xtensa xtreg ocd_dcrclr 0x2047
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xtensa xtreg ocd_dcrset 0x2048
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xtensa xtreg ocd_dsr 0x2049
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xtensa xtreg psintlevel 0x2003
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xtensa xtreg psum 0x2004
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xtensa xtreg pswoe 0x2005
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xtensa xtreg psexcm 0x2006
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xtensa xtreg pscallinc 0x2007
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xtensa xtreg psowb 0x2008
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