zy1000: FPGA revC wip
The bug in revC register memory access is pretty much cornered now. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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@ -18,6 +18,7 @@
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***************************************************************************/
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***************************************************************************/
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#include <cyg/hal/hal_io.h> // low level i/o
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#include <cyg/hal/hal_io.h> // low level i/o
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#include <cyg/hal/hal_intr.h> // low level i/o
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//#define VERBOSE(a) a
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//#define VERBOSE(a) a
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#define VERBOSE(a)
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#define VERBOSE(a)
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@ -31,10 +32,16 @@ int diag_printf(const char *fmt, ...);
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#define ZY1000_PEEK(a, b) HAL_READ_UINT32(a, b); diag_printf("peek 0x%08x = 0x%08x\n", a, b)
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#define ZY1000_PEEK(a, b) HAL_READ_UINT32(a, b); diag_printf("peek 0x%08x = 0x%08x\n", a, b)
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#else
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#else
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#define ZY1000_PEEK(a, b) HAL_READ_UINT32(a, b)
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#define ZY1000_PEEK(a, b) HAL_READ_UINT32(a, b)
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#define ZY1000_POKE(a, b) HAL_WRITE_UINT32(a, b);\
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{/* This will flush the bridge FIFO. Overflowed bridge FIFO fails. We must \
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#ifdef CYGPKG_HAL_NIOS2
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flush every "often". No precise system has been found, but 4 seems solid. \
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#define ZY1000_POKE(a, b) \
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*/ \
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{/* This will flush the bridge FIFO. Overflowed bridge FIFO fails. We must \
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flush every "often". No precise system has been found, but 4 seems solid. \
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This code goes away once the FPGA has been fixed. */ \
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\
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CYG_INTERRUPT_STATE _old_; \
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HAL_DISABLE_INTERRUPTS(_old_); \
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HAL_WRITE_UINT32(a, b);\
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static int overflow_counter = 0; \
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static int overflow_counter = 0; \
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if (++overflow_counter >= 1) \
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if (++overflow_counter >= 1) \
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{ \
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{ \
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@ -42,7 +49,14 @@ int diag_printf(const char *fmt, ...);
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cyg_uint32 empty; ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, empty); \
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cyg_uint32 empty; ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, empty); \
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overflow_counter = 0; \
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overflow_counter = 0; \
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} \
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} \
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}
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/* NB! interrupts must be restored *after* read */ \
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HAL_RESTORE_INTERRUPTS(_old_); \
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}\
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#else
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#define ZY1000_POKE(a, b) HAL_WRITE_UINT32(a, b)
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#endif
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#endif
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#endif
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// FIFO empty?
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// FIFO empty?
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