Reading v* registers appears to work.
Can't really test it though, because gdb doesn't print them right. Change-Id: I8d66339371c564a493d32f15c3d114b738a455c5
This commit is contained in:
Tim Newsome
parent
9e80ab1f85
commit
23a0ce22cf
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@ -56,7 +56,8 @@ int riscv_program_exec(struct riscv_program *p, struct target *t)
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if (riscv_program_ebreak(p) != ERROR_OK) {
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LOG_ERROR("Unable to write ebreak");
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for (size_t i = 0; i < riscv_debug_buffer_size(p->target); ++i)
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LOG_ERROR("ram[%02x]: DASM(0x%08lx) [0x%08lx]", (int)i, (long)p->debug_buffer[i], (long)p->debug_buffer[i]);
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LOG_ERROR("ram[%02x]: DASM(0x%08lx) [0x%08lx]", (int)i,
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(long)p->debug_buffer[i], (long)p->debug_buffer[i]);
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return ERROR_FAIL;
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}
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@ -1055,6 +1055,54 @@ static int examine_progbuf(struct target *target)
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return ERROR_OK;
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}
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static int is_fpu_reg(uint32_t gdb_regno)
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{
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return (gdb_regno >= GDB_REGNO_FPR0 && gdb_regno <= GDB_REGNO_FPR31) ||
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(gdb_regno == GDB_REGNO_CSR0 + CSR_FFLAGS) ||
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(gdb_regno == GDB_REGNO_CSR0 + CSR_FRM) ||
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(gdb_regno == GDB_REGNO_CSR0 + CSR_FCSR);
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}
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static int is_vector_reg(uint32_t gdb_regno)
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{
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return (gdb_regno >= GDB_REGNO_V0 && gdb_regno <= GDB_REGNO_V31) ||
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gdb_regno == GDB_REGNO_VSTART ||
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gdb_regno == GDB_REGNO_VXSAT ||
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gdb_regno == GDB_REGNO_VXRM ||
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gdb_regno == GDB_REGNO_VL ||
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gdb_regno == GDB_REGNO_VTYPE ||
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gdb_regno == GDB_REGNO_VLENB;
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}
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int prep_for_register_access(struct target *target, uint64_t *mstatus,
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int regno)
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{
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if (is_fpu_reg(regno) || is_vector_reg(regno)) {
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if (register_read(target, mstatus, GDB_REGNO_MSTATUS) != ERROR_OK)
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return ERROR_FAIL;
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if (is_fpu_reg(regno) && (*mstatus & MSTATUS_FS) == 0) {
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if (register_write_direct(target, GDB_REGNO_MSTATUS,
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set_field(*mstatus, MSTATUS_FS, 1)) != ERROR_OK)
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return ERROR_FAIL;
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} else if (is_vector_reg(regno) && (*mstatus & MSTATUS_VS) == 0) {
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if (register_write_direct(target, GDB_REGNO_MSTATUS,
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set_field(*mstatus, MSTATUS_VS, 1)) != ERROR_OK)
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return ERROR_FAIL;
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}
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}
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return ERROR_OK;
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}
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int cleanup_after_register_access(struct target *target, uint64_t mstatus,
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int regno)
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{
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if ((is_fpu_reg(regno) && (mstatus & MSTATUS_FS) == 0) ||
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(is_vector_reg(regno) && (mstatus & MSTATUS_VS) == 0))
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if (register_write_direct(target, GDB_REGNO_MSTATUS, mstatus) != ERROR_OK)
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return ERROR_FAIL;
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return ERROR_OK;
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}
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typedef enum {
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SPACE_DMI_DATA,
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SPACE_DMI_PROGBUF,
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@ -1253,6 +1301,10 @@ static int register_write_direct(struct target *target, unsigned number,
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if (register_read(target, &s0, GDB_REGNO_S0) != ERROR_OK)
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return ERROR_FAIL;
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uint64_t mstatus;
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if (prep_for_register_access(target, &mstatus, number) != ERROR_OK)
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return ERROR_FAIL;
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scratch_mem_t scratch;
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bool use_scratch = false;
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if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31 &&
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@ -1277,6 +1329,10 @@ static int register_write_direct(struct target *target, unsigned number,
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return ERROR_FAIL;
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}
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} else if (number == GDB_REGNO_VTYPE) {
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riscv_program_insert(&program, csrr(S0, CSR_VL));
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riscv_program_insert(&program, vsetvli(ZERO, S0, value));
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} else {
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if (register_write_direct(target, GDB_REGNO_S0, value) != ERROR_OK)
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return ERROR_FAIL;
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@ -1313,6 +1369,9 @@ static int register_write_direct(struct target *target, unsigned number,
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if (use_scratch)
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scratch_release(target, &scratch);
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if (cleanup_after_register_access(target, mstatus, number) != ERROR_OK)
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return ERROR_FAIL;
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/* Restore S0. */
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if (register_write_direct(target, GDB_REGNO_S0, s0) != ERROR_OK)
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return ERROR_FAIL;
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@ -1337,25 +1396,6 @@ static int register_read(struct target *target, uint64_t *value, uint32_t number
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return ERROR_OK;
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}
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static int is_fpu_reg(uint32_t gdb_regno)
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{
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return (gdb_regno >= GDB_REGNO_FPR0 && gdb_regno <= GDB_REGNO_FPR31) ||
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(gdb_regno == GDB_REGNO_CSR0 + CSR_FFLAGS) ||
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(gdb_regno == GDB_REGNO_CSR0 + CSR_FRM) ||
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(gdb_regno == GDB_REGNO_CSR0 + CSR_FCSR);
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}
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static int is_vector_reg(uint32_t gdb_regno)
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{
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return (gdb_regno >= GDB_REGNO_V0 && gdb_regno <= GDB_REGNO_V31) ||
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gdb_regno == GDB_REGNO_VSTART ||
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gdb_regno == GDB_REGNO_VXSAT ||
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gdb_regno == GDB_REGNO_VXRM ||
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gdb_regno == GDB_REGNO_VL ||
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gdb_regno == GDB_REGNO_VTYPE ||
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gdb_regno == GDB_REGNO_VLENB;
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}
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/** Actually read registers from the target right now. */
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static int register_read_direct(struct target *target, uint64_t *value, uint32_t number)
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{
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@ -1381,19 +1421,8 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t
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/* Write program to move data into s0. */
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uint64_t mstatus;
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if (is_fpu_reg(number) || is_vector_reg(number)) {
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if (register_read(target, &mstatus, GDB_REGNO_MSTATUS) != ERROR_OK)
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return ERROR_FAIL;
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if (is_fpu_reg(number) && (mstatus & MSTATUS_FS) == 0) {
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if (register_write_direct(target, GDB_REGNO_MSTATUS,
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set_field(mstatus, MSTATUS_FS, 1)) != ERROR_OK)
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return ERROR_FAIL;
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} else if (is_vector_reg(number) && (mstatus & MSTATUS_VS) == 0) {
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if (register_write_direct(target, GDB_REGNO_MSTATUS,
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set_field(mstatus, MSTATUS_VS, 1)) != ERROR_OK)
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return ERROR_FAIL;
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}
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}
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if (prep_for_register_access(target, &mstatus, number) != ERROR_OK)
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return ERROR_FAIL;
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if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
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if (riscv_supports_extension(target, riscv_current_hartid(target), 'D')
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@ -1420,78 +1449,6 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t
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}
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} else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
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riscv_program_csrr(&program, S0, number);
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} else if (number >= GDB_REGNO_V0 && number <= GDB_REGNO_V31) {
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/*
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* The idea is that you read a vector register destructively: read
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* element 0 using vmv.x.s into t0; send t0 to the debugger; then
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* vslide1down with t0 as the scalar argument. This is effectively
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* rotating the vector one element at a time, so after vl steps,
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* the vector register is back to its original value."
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*
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* The two instructions vmv.x.s and vmv.s.x are described in
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* section 17.1.
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*
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* The vmv.x.s instruction copies a single SEW-wide element from
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* index 0 of the source vector register to a destination integer
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* register.
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*
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* The vmv.s.x instruction copies the scalar integer register to
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* element 0 of the destination vector register.
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*
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* Executing the two instructions in the PROGBUF and reading or
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* writing the x register in a loop would not be that much slower
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* than executing the instruction to move a vector reg to memory
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* then reading memory sequentially.
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*
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* I recommend not using memory-based vector register read/writes -
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* it would add user complication to have to allocate target memory
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* for a vector register buffer just for debug - and require adding
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* to the linker script to do this allocation and then informing
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* the debugger where it is. */
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/* TODO: this continuous save/restore is terrible for performance. */
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uint64_t vtype, vl;
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/* Save vtype and vl. */
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if (register_read(target, &vtype, GDB_REGNO_VTYPE) != ERROR_OK)
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return ERROR_FAIL;
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if (register_read(target, &vl, GDB_REGNO_VL) != ERROR_OK)
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return ERROR_FAIL;
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/* Restore vtype and vl. */
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unsigned encoded_vsew;
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switch (riscv_xlen(target)) {
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case 32:
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encoded_vsew = 2;
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break;
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case 64:
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encoded_vsew = 3;
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break;
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default:
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LOG_ERROR("Unsupported xlen: %d", riscv_xlen(target));
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return ERROR_FAIL;
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}
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if (register_write_direct(target, GDB_REGNO_VTYPE, encoded_vsew << 2) != ERROR_OK)
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return ERROR_FAIL;
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unsigned debug_vl = DIV_ROUND_UP(r->vlenb[r->current_hartid] * 8,
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riscv_xlen(target));
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if (register_write_direct(target, GDB_REGNO_VL, debug_vl) != ERROR_OK)
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return ERROR_FAIL;
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unsigned vnum = number - GDB_REGNO_V0;
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riscv_program_insert(&program, vmv_x_s(S0, vnum));
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riscv_program_insert(&program, vslide1down_vx(vnum, vnum, S0, false));
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for (unsigned i = 0; i < debug_vl; i++) {
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if (riscv_program_exec(&program, target) != ERROR_OK)
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return ERROR_FAIL;
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if (register_read_direct(target, value, GDB_REGNO_S0) != ERROR_OK)
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return ERROR_FAIL;
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}
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/* Restore vtype and vl. */
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if (register_write_direct(target, GDB_REGNO_VTYPE, vtype) != ERROR_OK)
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return ERROR_FAIL;
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if (register_write_direct(target, GDB_REGNO_VL, vl) != ERROR_OK)
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return ERROR_FAIL;
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} else {
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LOG_ERROR("Unsupported register: %s", gdb_regno_name(number));
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return ERROR_FAIL;
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@ -1512,10 +1469,8 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t
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return ERROR_FAIL;
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}
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if ((is_fpu_reg(number) && (mstatus & MSTATUS_FS) == 0) ||
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(is_vector_reg(number) && (mstatus & MSTATUS_VS) == 0))
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if (register_write_direct(target, GDB_REGNO_MSTATUS, mstatus) != ERROR_OK)
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return ERROR_FAIL;
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if (cleanup_after_register_access(target, mstatus, number) != ERROR_OK)
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return ERROR_FAIL;
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/* Restore S0. */
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if (register_write_direct(target, GDB_REGNO_S0, s0) != ERROR_OK)
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@ -1881,6 +1836,114 @@ static unsigned riscv013_data_bits(struct target *target)
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return riscv_xlen(target);
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}
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static int riscv013_get_register_buf(struct target *target,
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uint8_t *value, int regno)
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{
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RISCV_INFO(r);
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assert(regno >= GDB_REGNO_V0 && regno <= GDB_REGNO_V31);
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riscv_reg_t s0;
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if (register_read(target, &s0, GDB_REGNO_S0) != ERROR_OK)
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return ERROR_FAIL;
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uint64_t mstatus;
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if (prep_for_register_access(target, &mstatus, regno) != ERROR_OK)
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return ERROR_FAIL;
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/*
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* The idea is that you read a vector register destructively: read
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* element 0 using vmv.x.s into t0; send t0 to the debugger; then
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* vslide1down with t0 as the scalar argument. This is effectively
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* rotating the vector one element at a time, so after vl steps,
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* the vector register is back to its original value."
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*
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* The two instructions vmv.x.s and vmv.s.x are described in
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* section 17.1.
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*
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* The vmv.x.s instruction copies a single SEW-wide element from
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* index 0 of the source vector register to a destination integer
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* register.
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*
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* The vmv.s.x instruction copies the scalar integer register to
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* element 0 of the destination vector register.
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*
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* Executing the two instructions in the PROGBUF and reading or
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* writing the x register in a loop would not be that much slower
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* than executing the instruction to move a vector reg to memory
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* then reading memory sequentially.
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*
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* I recommend not using memory-based vector register read/writes -
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* it would add user complication to have to allocate target memory
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* for a vector register buffer just for debug - and require adding
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* to the linker script to do this allocation and then informing
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* the debugger where it is. */
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/* TODO: this continuous save/restore is terrible for performance. */
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uint64_t vtype, vl;
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/* Save vtype and vl. */
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if (register_read(target, &vtype, GDB_REGNO_VTYPE) != ERROR_OK)
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return ERROR_FAIL;
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if (register_read(target, &vl, GDB_REGNO_VL) != ERROR_OK)
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return ERROR_FAIL;
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/* Write vtype and vl. */
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unsigned encoded_vsew;
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switch (riscv_xlen(target)) {
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case 32:
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encoded_vsew = 2;
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break;
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case 64:
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encoded_vsew = 3;
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break;
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default:
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LOG_ERROR("Unsupported xlen: %d", riscv_xlen(target));
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return ERROR_FAIL;
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}
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if (register_write_direct(target, GDB_REGNO_VTYPE, encoded_vsew << 2) != ERROR_OK)
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return ERROR_FAIL;
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unsigned debug_vl = DIV_ROUND_UP(r->vlenb[r->current_hartid] * 8,
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riscv_xlen(target));
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if (register_write_direct(target, GDB_REGNO_VL, debug_vl) != ERROR_OK)
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return ERROR_FAIL;
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unsigned vnum = regno - GDB_REGNO_V0;
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unsigned xlen = riscv_xlen(target);
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struct riscv_program program;
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riscv_program_init(&program, target);
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riscv_program_insert(&program, vmv_x_s(S0, vnum));
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riscv_program_insert(&program, vslide1down_vx(vnum, vnum, S0, false));
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for (unsigned i = 0; i < debug_vl; i++) {
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if (riscv_program_exec(&program, target) != ERROR_OK)
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return ERROR_FAIL;
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uint64_t v;
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if (register_read_direct(target, &v, GDB_REGNO_S0) != ERROR_OK)
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return ERROR_FAIL;
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buf_set_u64(value, xlen * i, xlen, v);
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}
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/* Restore vtype and vl. */
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if (register_write_direct(target, GDB_REGNO_VTYPE, vtype) != ERROR_OK)
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return ERROR_FAIL;
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if (register_write_direct(target, GDB_REGNO_VL, vl) != ERROR_OK)
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return ERROR_FAIL;
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if (cleanup_after_register_access(target, mstatus, regno) != ERROR_OK)
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return ERROR_FAIL;
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if (register_write_direct(target, GDB_REGNO_S0, s0) != ERROR_OK)
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return ERROR_FAIL;
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return ERROR_OK;
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}
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static int riscv013_set_register_buf(struct target *target,
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int regno, const uint8_t *value)
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{
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assert(regno >= GDB_REGNO_V0 && regno <= GDB_REGNO_V31);
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return ERROR_FAIL;
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}
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static int init_target(struct command_context *cmd_ctx,
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struct target *target)
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{
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@ -1889,6 +1952,8 @@ static int init_target(struct command_context *cmd_ctx,
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generic_info->get_register = &riscv013_get_register;
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generic_info->set_register = &riscv013_set_register;
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generic_info->get_register_buf = &riscv013_get_register_buf;
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generic_info->set_register_buf = &riscv013_set_register_buf;
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generic_info->select_current_hart = &riscv013_select_current_hart;
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generic_info->is_halted = &riscv013_is_halted;
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generic_info->resume_go = &riscv013_resume_go;
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@ -3505,10 +3570,12 @@ static int riscv013_get_register(struct target *target,
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int result = ERROR_OK;
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if (rid == GDB_REGNO_PC) {
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/* TODO: move this into riscv.c. */
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result = register_read(target, value, GDB_REGNO_DPC);
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LOG_DEBUG("[%d] read PC from DPC: 0x%" PRIx64, target->coreid, *value);
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} else if (rid == GDB_REGNO_PRIV) {
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uint64_t dcsr;
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/* TODO: move this into riscv.c. */
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result = register_read(target, &dcsr, GDB_REGNO_DCSR);
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*value = get_field(dcsr, CSR_DCSR_PRV);
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} else {
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@ -3229,6 +3229,10 @@ const char *gdb_regno_name(enum gdb_regno regno)
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return "priv";
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case GDB_REGNO_SATP:
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return "satp";
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case GDB_REGNO_VTYPE:
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return "vtype";
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case GDB_REGNO_VL:
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return "vl";
|
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case GDB_REGNO_V0:
|
||||
return "v0";
|
||||
case GDB_REGNO_V1:
|
||||
|
|
@ -3310,20 +3314,35 @@ static int register_get(struct reg *reg)
|
|||
{
|
||||
riscv_reg_info_t *reg_info = reg->arch_info;
|
||||
struct target *target = reg_info->target;
|
||||
uint64_t value;
|
||||
int result = riscv_get_register(target, &value, reg->number);
|
||||
if (result != ERROR_OK)
|
||||
return result;
|
||||
buf_set_u64(reg->value, 0, reg->size, value);
|
||||
RISCV_INFO(r);
|
||||
|
||||
if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
|
||||
if (!r->get_register_buf) {
|
||||
LOG_ERROR("Reading register %s not supported on this RISC-V target.",
|
||||
gdb_regno_name(reg->number));
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
if (r->get_register_buf(target, reg->value, reg->number) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
} else {
|
||||
uint64_t value;
|
||||
int result = riscv_get_register(target, &value, reg->number);
|
||||
if (result != ERROR_OK)
|
||||
return result;
|
||||
buf_set_u64(reg->value, 0, reg->size, value);
|
||||
}
|
||||
/* CSRs (and possibly other extension) registers may change value at any
|
||||
* time. */
|
||||
if (reg->number <= GDB_REGNO_XPR31 ||
|
||||
(reg->number >= GDB_REGNO_FPR0 && reg->number <= GDB_REGNO_FPR31) ||
|
||||
(reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) ||
|
||||
reg->number == GDB_REGNO_PC)
|
||||
reg->valid = true;
|
||||
LOG_DEBUG("[%d]{%d} read 0x%" PRIx64 " from %s (valid=%d)",
|
||||
target->coreid, riscv_current_hartid(target), value, reg->name,
|
||||
reg->valid);
|
||||
char *str = buf_to_str(reg->value, reg->size, 16);
|
||||
LOG_DEBUG("[%d]{%d} read 0x%s from %s (valid=%d)", target->coreid,
|
||||
riscv_current_hartid(target), str, reg->name, reg->valid);
|
||||
free(str);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
@ -3331,22 +3350,37 @@ static int register_set(struct reg *reg, uint8_t *buf)
|
|||
{
|
||||
riscv_reg_info_t *reg_info = reg->arch_info;
|
||||
struct target *target = reg_info->target;
|
||||
RISCV_INFO(r);
|
||||
|
||||
uint64_t value = buf_get_u64(buf, 0, reg->size);
|
||||
char *str = buf_to_str(reg->value, reg->size, 16);
|
||||
LOG_DEBUG("[%d]{%d} write 0x%s to %s (valid=%d)", target->coreid,
|
||||
riscv_current_hartid(target), str, reg->name, reg->valid);
|
||||
free(str);
|
||||
|
||||
LOG_DEBUG("[%d]{%d} write 0x%" PRIx64 " to %s (valid=%d)",
|
||||
target->coreid, riscv_current_hartid(target), value, reg->name,
|
||||
reg->valid);
|
||||
struct reg *r = &target->reg_cache->reg_list[reg->number];
|
||||
memcpy(reg->value, buf, DIV_ROUND_UP(reg->size, 8));
|
||||
/* CSRs (and possibly other extension) registers may change value at any
|
||||
* time. */
|
||||
if (reg->number <= GDB_REGNO_XPR31 ||
|
||||
(reg->number >= GDB_REGNO_FPR0 && reg->number <= GDB_REGNO_FPR31) ||
|
||||
(reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) ||
|
||||
reg->number == GDB_REGNO_PC)
|
||||
r->valid = true;
|
||||
memcpy(r->value, buf, (r->size + 7) / 8);
|
||||
reg->valid = true;
|
||||
|
||||
if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
|
||||
if (!r->set_register_buf) {
|
||||
LOG_ERROR("Reading register %s not supported on this RISC-V target.",
|
||||
gdb_regno_name(reg->number));
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
if (r->set_register_buf(target, reg->number, reg->value) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
} else {
|
||||
uint64_t value = buf_get_u64(buf, 0, reg->size);
|
||||
if (riscv_set_register(target, reg->number, value) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
riscv_set_register(target, reg->number, value);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
@ -3835,9 +3869,11 @@ int riscv_init_registers(struct target *target)
|
|||
r->size = 8;
|
||||
|
||||
} else if (number >= GDB_REGNO_V0 && number <= GDB_REGNO_V31) {
|
||||
r->caller_save = true;
|
||||
/* TODO: These should be caller saved, but if I say it's true then
|
||||
* gdb only tries to save 32 bits, which makes OpenOCD unhappy when
|
||||
* it tries to write a 32-bit value to a larger register. */
|
||||
r->caller_save = false;
|
||||
r->exist = riscv_supports_extension(target, hartid, 'V');
|
||||
//r->reg_data_type = &type_arch_defined;
|
||||
r->size = info->vlenb[hartid] * 8;
|
||||
sprintf(reg_name, "v%d", number - GDB_REGNO_V0);
|
||||
r->group = "vector";
|
||||
|
|
|
|||
|
|
@ -111,6 +111,9 @@ typedef struct {
|
|||
riscv_reg_t *value, int hid, int rid);
|
||||
int (*set_register)(struct target *, int hartid, int regid,
|
||||
uint64_t value);
|
||||
int (*get_register_buf)(struct target *target, uint8_t *buf, int regno);
|
||||
int (*set_register_buf)(struct target *target, int regno,
|
||||
const uint8_t *buf);
|
||||
int (*select_current_hart)(struct target *);
|
||||
bool (*is_halted)(struct target *target);
|
||||
/* Resume this target, as well as every other prepped target that can be
|
||||
|
|
|
|||
Loading…
Reference in New Issue