target/riscv: add nuclei custom csrs in encoding.h

Change-Id: I335be71f5d8ff837998edece2947ea6e48f0dbf3
Signed-off-by: wangyanwen <wangyanwen@nucleisys.com>

src/target/riscv/encoding.h

@@ -3212,6 +3212,142 @@
 #define CSR_MHPMCOUNTER30H 0xb9e
 #define CSR_MHPMCOUNTER31H 0xb9f
 
+/* === TEE CSR Registers === */
+#define CSR_SPMPCFG0 0x1a0
+#define CSR_SPMPCFG1 0x1a1
+#define CSR_SPMPCFG2 0x1a2
+#define CSR_SPMPCFG3 0x1a3
+#define CSR_SPMPADDR0 0x1b0
+#define CSR_SPMPADDR1 0x1b1
+#define CSR_SPMPADDR2 0x1b2
+#define CSR_SPMPADDR3 0x1b3
+#define CSR_SPMPADDR4 0x1b4
+#define CSR_SPMPADDR5 0x1b5
+#define CSR_SPMPADDR6 0x1b6
+#define CSR_SPMPADDR7 0x1b7
+#define CSR_SPMPADDR8 0x1b8
+#define CSR_SPMPADDR9 0x1b9
+#define CSR_SPMPADDR10 0x1ba
+#define CSR_SPMPADDR11 0x1bb
+#define CSR_SPMPADDR12 0x1bc
+#define CSR_SPMPADDR13 0x1bd
+#define CSR_SPMPADDR14 0x1be
+#define CSR_SPMPADDR15 0x1bf
+#define CSR_SMPUSWITCH0 0x170
+#define CSR_SMPUSWITCH1 0x171
+
+/* === Nuclei custom CSR Registers === */
+#define CSR_MILM_CTL 0x7c0
+#define CSR_MDLM_CTL 0x7c1
+#define CSR_MECC_CODE 0x7c2
+#define CSR_MNVEC 0x7c3
+#define CSR_MSUBM 0x7c4
+#define CSR_MDCAUSE 0x7c9
+#define CSR_MCACHE_CTL 0x7ca
+#define CSR_MMISC_CTL 0x7d0
+#define CSR_MSAVESTATUS 0x7d6
+#define CSR_MSAVEEPC1 0x7d7
+#define CSR_MSAVECAUSE1 0x7d8
+#define CSR_MSAVEEPC2 0x7d9
+#define CSR_MSAVECAUSE2 0x7da
+#define CSR_MSAVEDCAUSE1 0x7db
+#define CSR_MSAVEDCAUSE2 0x7dc
+#define CSR_MTLB_CTL 0x7dd
+#define CSR_MECC_LOCK 0x7de
+#define CSR_MFP16MODE 0x7e2
+#define CSR_LSTEPFORC 0x7e9
+#define CSR_PUSHMSUBM 0x7eb
+#define CSR_MTVT2 0x7ec
+#define CSR_JALMNXTI 0x7ed
+#define CSR_PUSHMCAUSE 0x7ee
+#define CSR_PUSHMEPC 0x7ef
+#define CSR_MPPICFG_INFO 0x7f0
+#define CSR_MFIOCFG_INFO 0x7f1
+#define CSR_MATTRI0_BASE 0x7f3
+#define CSR_MATTRI0_MASK 0x7f4
+#define CSR_MATTRI1_BASE 0x7f5
+#define CSR_MATTRI1_MASK 0x7f6
+#define CSR_MATTRI2_BASE 0x7f9
+#define CSR_MATTRI2_MASK 0x7fa
+#define CSR_MATTRI3_BASE 0x7fb
+#define CSR_MATTRI3_MASK 0x7fc
+#define CSR_MATTRI4_BASE 0x7fd
+#define CSR_MATTRI4_MASK 0x7fe
+#define CSR_MIRGB_INFO 0x7f7
+#define CSR_SLEEPVALUE 0x811
+#define CSR_TXEVT 0x812
+#define CSR_SAFETY_CRC_CTL 0x813
+#define CSR_SAFETY_STL_STATUS 0x814
+#define CSR_WFE 0x810
+#define CSR_JALSNXTI 0x947
+#define CSR_STVT2 0x948
+#define CSR_PUSHSCAUSE 0x949
+#define CSR_PUSHSEPC 0x94a
+#define CSR_SDCAUSE 0x9c0
+#define CSR_MICFG_INFO 0xfc0
+#define CSR_MDCFG_INFO 0xfc1
+#define CSR_MCFG_INFO 0xfc2
+#define CSR_MTLBCFG_INFO 0xfc3
+#define CSR_MECC_CTL 0xbc0
+#define CSR_MECC_STATUS 0xbc4
+#define CSR_MMACRO_DEV_EN 0xbc8
+#define CSR_MMACRO_NOC_EN 0xbc9
+#define CSR_MMACRO_CA_EN 0xbca
+#define CSR_IRQCIP 0xbd0
+#define CSR_IRQCIE 0xbd1
+#define CSR_IRQCLVL 0xbd2
+#define CSR_IRQCEDGE 0xbd3
+#define CSR_IRQCINFO 0xbd4
+#define CSR_MSIP 0xbd8
+#define CSR_MTIMECMP 0xbd9
+#define CSR_MTIME 0xbda
+#define CSR_MSTOP 0xbdb
+#define CSR_MATTRI5_BASE 0xbe0
+#define CSR_MATTRI5_MASK 0xbe1
+#define CSR_MATTRI6_BASE 0xbe2
+#define CSR_MATTRI6_MASK 0xbe3
+#define CSR_MATTRI7_BASE 0xbe4
+#define CSR_MATTRI7_MASK 0xbe5
+
+/* === P-Extension Registers === */
+#define CSR_UCODE 0x801
+
+/* === Nuclei CCM Registers === */
+#define CSR_CCM_MBEGINADDR 0x7cb
+#define CSR_CCM_MCOMMAND 0x7cc
+#define CSR_CCM_MDATA 0x7cd
+#define CSR_CCM_SUEN 0x7ce
+#define CSR_CCM_SBEGINADDR 0x5cb
+#define CSR_CCM_SCOMMAND 0x5cc
+#define CSR_CCM_SDATA 0x5cd
+#define CSR_CCM_UBEGINADDR 0x4cb
+#define CSR_CCM_UCOMMAND 0x4cc
+#define CSR_CCM_UDATA 0x4cd
+#define CSR_CCM_FPIPE 0x4cf
+
+/* === Nuclei Supervisor Registers === */
+#define CSR_SATTRI0_BASE 0x5f0
+#define CSR_SATTRI0_MASK 0x5f1
+#define CSR_SATTRI1_BASE 0x5f2
+#define CSR_SATTRI1_MASK 0x5f3
+#define CSR_SATTRI2_BASE 0x5f4
+#define CSR_SATTRI2_MASK 0x5f5
+#define CSR_SATTRI3_BASE 0x5f6
+#define CSR_SATTRI3_MASK 0x5f7
+#define CSR_SATTRI4_BASE 0x5f8
+#define CSR_SATTRI4_MASK 0x5f9
+#define CSR_SATTRI5_BASE 0x5fa
+#define CSR_SATTRI5_MASK 0x5fb
+#define CSR_SATTRI6_BASE 0x5fc
+#define CSR_SATTRI6_MASK 0x5fd
+#define CSR_SATTRI7_BASE 0x5fe
+#define CSR_SATTRI7_MASK 0x5ff
+
+/* === Nuclei Stack Checker Registers === */
+#define CSR_MSTACK_CTL 0x7c6
+#define CSR_MSTACK_BOUND 0x7c7
+#define CSR_MSTACK_BASE 0x7c8
+
 #define CAUSE_MISALIGNED_FETCH 0x0
 #define CAUSE_FETCH_ACCESS 0x1
 #define CAUSE_ILLEGAL_INSTRUCTION 0x2
@@ -4968,6 +5104,143 @@ DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
 DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
 DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
 DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+
+/* === TEE CSR Registers === */
+DECLARE_CSR(spmpcfg0, CSR_SPMPCFG0)
+DECLARE_CSR(spmpcfg1, CSR_SPMPCFG1)
+DECLARE_CSR(spmpcfg2, CSR_SPMPCFG2)
+DECLARE_CSR(spmpcfg3, CSR_SPMPCFG3)
+DECLARE_CSR(spmpaddr0, CSR_SPMPADDR0)
+DECLARE_CSR(spmpaddr1, CSR_SPMPADDR1)
+DECLARE_CSR(spmpaddr2, CSR_SPMPADDR2)
+DECLARE_CSR(spmpaddr3, CSR_SPMPADDR3)
+DECLARE_CSR(spmpaddr4, CSR_SPMPADDR4)
+DECLARE_CSR(spmpaddr5, CSR_SPMPADDR5)
+DECLARE_CSR(spmpaddr6, CSR_SPMPADDR6)
+DECLARE_CSR(spmpaddr7, CSR_SPMPADDR7)
+DECLARE_CSR(spmpaddr8, CSR_SPMPADDR8)
+DECLARE_CSR(spmpaddr9, CSR_SPMPADDR9)
+DECLARE_CSR(spmpaddr10, CSR_SPMPADDR10)
+DECLARE_CSR(spmpaddr11, CSR_SPMPADDR11)
+DECLARE_CSR(spmpaddr12, CSR_SPMPADDR12)
+DECLARE_CSR(spmpaddr13, CSR_SPMPADDR13)
+DECLARE_CSR(spmpaddr14, CSR_SPMPADDR14)
+DECLARE_CSR(spmpaddr15, CSR_SPMPADDR15)
+DECLARE_CSR(smpuswitch0, CSR_SMPUSWITCH0)
+DECLARE_CSR(smpuswitch1, CSR_SMPUSWITCH1)
+
+/* === Nuclei custom CSR Registers === */
+DECLARE_CSR(milm_ctl, CSR_MILM_CTL)
+DECLARE_CSR(mdlm_ctl, CSR_MDLM_CTL)
+DECLARE_CSR(mecc_code, CSR_MECC_CODE)
+DECLARE_CSR(mnvec, CSR_MNVEC)
+DECLARE_CSR(msubm, CSR_MSUBM)
+DECLARE_CSR(mdcause, CSR_MDCAUSE)
+DECLARE_CSR(mcache_ctl, CSR_MCACHE_CTL)
+DECLARE_CSR(mmisc_ctl, CSR_MMISC_CTL)
+DECLARE_CSR(msavestatus, CSR_MSAVESTATUS)
+DECLARE_CSR(msaveepc1, CSR_MSAVEEPC1)
+DECLARE_CSR(msavecause1, CSR_MSAVECAUSE1)
+DECLARE_CSR(msaveepc2, CSR_MSAVEEPC2)
+DECLARE_CSR(msavecause2, CSR_MSAVECAUSE2)
+DECLARE_CSR(msavedcause1, CSR_MSAVEDCAUSE1)
+DECLARE_CSR(msavedcause2, CSR_MSAVEDCAUSE2)
+DECLARE_CSR(mtlb_ctl, CSR_MTLB_CTL)
+DECLARE_CSR(mecc_lock, CSR_MECC_LOCK)
+DECLARE_CSR(mfp16mode, CSR_MFP16MODE)
+DECLARE_CSR(lstepforc, CSR_LSTEPFORC)
+DECLARE_CSR(pushmsubm, CSR_PUSHMSUBM)
+DECLARE_CSR(mtvt2, CSR_MTVT2)
+DECLARE_CSR(jalmnxti, CSR_JALMNXTI)
+DECLARE_CSR(pushmcause, CSR_PUSHMCAUSE)
+DECLARE_CSR(pushmepc, CSR_PUSHMEPC)
+DECLARE_CSR(mppicfg_info, CSR_MPPICFG_INFO)
+DECLARE_CSR(mfiocfg_info, CSR_MFIOCFG_INFO)
+DECLARE_CSR(mattri0_base, CSR_MATTRI0_BASE)
+DECLARE_CSR(mattri0_mask, CSR_MATTRI0_MASK)
+DECLARE_CSR(mattri1_base, CSR_MATTRI1_BASE)
+DECLARE_CSR(mattri1_mask, CSR_MATTRI1_MASK)
+DECLARE_CSR(mattri2_base, CSR_MATTRI2_BASE)
+DECLARE_CSR(mattri2_mask, CSR_MATTRI2_MASK)
+DECLARE_CSR(mattri3_base, CSR_MATTRI3_BASE)
+DECLARE_CSR(mattri3_mask, CSR_MATTRI3_MASK)
+DECLARE_CSR(mattri4_base, CSR_MATTRI4_BASE)
+DECLARE_CSR(mattri4_mask, CSR_MATTRI4_MASK)
+DECLARE_CSR(mirgb_info, CSR_MIRGB_INFO)
+DECLARE_CSR(sleepvalue, CSR_SLEEPVALUE)
+DECLARE_CSR(txevt, CSR_TXEVT)
+DECLARE_CSR(safety_crc_ctl, CSR_SAFETY_CRC_CTL)
+DECLARE_CSR(safety_stl_status, CSR_SAFETY_STL_STATUS)
+DECLARE_CSR(wfe, CSR_WFE)
+DECLARE_CSR(jalsnxti, CSR_JALSNXTI)
+DECLARE_CSR(stvt2, CSR_STVT2)
+DECLARE_CSR(pushscause, CSR_PUSHSCAUSE)
+DECLARE_CSR(pushsepc, CSR_PUSHSEPC)
+DECLARE_CSR(sdcause, CSR_SDCAUSE)
+DECLARE_CSR(micfg_info, CSR_MICFG_INFO)
+DECLARE_CSR(mdcfg_info, CSR_MDCFG_INFO)
+DECLARE_CSR(mcfg_info, CSR_MCFG_INFO)
+DECLARE_CSR(mtlbcfg_info, CSR_MTLBCFG_INFO)
+DECLARE_CSR(mecc_ctl, CSR_MECC_CTL)
+DECLARE_CSR(mecc_status, CSR_MECC_STATUS)
+DECLARE_CSR(mmacro_dev_en, CSR_MMACRO_DEV_EN)
+DECLARE_CSR(mmacro_noc_en, CSR_MMACRO_NOC_EN)
+DECLARE_CSR(mmacro_ca_en, CSR_MMACRO_CA_EN)
+DECLARE_CSR(irqcip, CSR_IRQCIP)
+DECLARE_CSR(irqcie, CSR_IRQCIE)
+DECLARE_CSR(irqclvl, CSR_IRQCLVL)
+DECLARE_CSR(irqcedge, CSR_IRQCEDGE)
+DECLARE_CSR(irqcinfo, CSR_IRQCINFO)
+DECLARE_CSR(msip, CSR_MSIP)
+DECLARE_CSR(mtimecmp, CSR_MTIMECMP)
+DECLARE_CSR(mtime, CSR_MTIME)
+DECLARE_CSR(mstop, CSR_MSTOP)
+DECLARE_CSR(mattri5_base, CSR_MATTRI5_BASE)
+DECLARE_CSR(mattri5_mask, CSR_MATTRI5_MASK)
+DECLARE_CSR(mattri6_base, CSR_MATTRI6_BASE)
+DECLARE_CSR(mattri6_mask, CSR_MATTRI6_MASK)
+DECLARE_CSR(mattri7_base, CSR_MATTRI7_BASE)
+DECLARE_CSR(mattri7_mask, CSR_MATTRI7_MASK)
+
+/* === P-Extension Registers === */
+DECLARE_CSR(ucode, CSR_UCODE)
+
+/* === Nuclei CCM Registers === */
+DECLARE_CSR(ccm_mbeginaddr, CSR_CCM_MBEGINADDR)
+DECLARE_CSR(ccm_mcommand, CSR_CCM_MCOMMAND)
+DECLARE_CSR(ccm_mdata, CSR_CCM_MDATA)
+DECLARE_CSR(ccm_suen, CSR_CCM_SUEN)
+DECLARE_CSR(ccm_sbeginaddr, CSR_CCM_SBEGINADDR)
+DECLARE_CSR(ccm_scommand, CSR_CCM_SCOMMAND)
+DECLARE_CSR(ccm_sdata, CSR_CCM_SDATA)
+DECLARE_CSR(ccm_ubeginaddr, CSR_CCM_UBEGINADDR)
+DECLARE_CSR(ccm_ucommand, CSR_CCM_UCOMMAND)
+DECLARE_CSR(ccm_udata, CSR_CCM_UDATA)
+DECLARE_CSR(ccm_fpipe, CSR_CCM_FPIPE)
+
+/* === Nuclei Supervisor Registers === */
+DECLARE_CSR(sattri0_base, CSR_SATTRI0_BASE)
+DECLARE_CSR(sattri0_mask, CSR_SATTRI0_MASK)
+DECLARE_CSR(sattri1_base, CSR_SATTRI1_BASE)
+DECLARE_CSR(sattri1_mask, CSR_SATTRI1_MASK)
+DECLARE_CSR(sattri2_base, CSR_SATTRI2_BASE)
+DECLARE_CSR(sattri2_mask, CSR_SATTRI2_MASK)
+DECLARE_CSR(sattri3_base, CSR_SATTRI3_BASE)
+DECLARE_CSR(sattri3_mask, CSR_SATTRI3_MASK)
+DECLARE_CSR(sattri4_base, CSR_SATTRI4_BASE)
+DECLARE_CSR(sattri4_mask, CSR_SATTRI4_MASK)
+DECLARE_CSR(sattri5_base, CSR_SATTRI5_BASE)
+DECLARE_CSR(sattri5_mask, CSR_SATTRI5_MASK)
+DECLARE_CSR(sattri6_base, CSR_SATTRI6_BASE)
+DECLARE_CSR(sattri6_mask, CSR_SATTRI6_MASK)
+DECLARE_CSR(sattri7_base, CSR_SATTRI7_BASE)
+DECLARE_CSR(sattri7_mask, CSR_SATTRI7_MASK)
+
+/* === Nuclei Stack Checker Registers === */
+DECLARE_CSR(mstack_ctl, CSR_MSTACK_CTL)
+DECLARE_CSR(mstack_bound, CSR_MSTACK_BOUND)
+DECLARE_CSR(mstack_base, CSR_MSTACK_BASE)
+
 #endif
 #ifdef DECLARE_CAUSE
 DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)