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target/riscv: Use macros for trigger types. 

Change-Id: I6ced3fb5a22bff4694fbceb8cf91f6cf6ce37ebf
Signed-off-by: Tim Newsome <tim@sifive.com>
This commit is contained in:
Tim Newsome 2022-12-27 12:53:52 -08:00
parent eb8bb957d4
commit 2258a59a0f
1 changed files with 6 additions and 6 deletions
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12
src/target/riscv/riscv.c
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@ -1071,13 +1071,13 @@ static int riscv_hit_trigger_hit_bit(struct target *target, uint32_t *unique_id)
uint64_t hit_mask = 0; uint64_t hit_mask = 0;
switch (type) { switch (type) {
case 1: case CSR_TDATA1_TYPE_LEGACY:
/* Doesn't support hit bit. */ /* Doesn't support hit bit. */
break; break;
case 2: case CSR_TDATA1_TYPE_MCONTROL:
hit_mask = CSR_MCONTROL_HIT; hit_mask = CSR_MCONTROL_HIT;
break; break;
case 6: case CSR_TDATA1_TYPE_MCONTROL6:
hit_mask = CSR_MCONTROL6_HIT; hit_mask = CSR_MCONTROL6_HIT;
break; break;
default: default:
@ -4120,16 +4120,16 @@ int riscv_enumerate_triggers(struct target *target)
if (type == 0) if (type == 0)
break; break;
switch (type) { switch (type) {
case 1: case CSR_TDATA1_TYPE_LEGACY:
/* On these older cores we don't support software using /* On these older cores we don't support software using
* triggers. */ * triggers. */
riscv_set_register(target, GDB_REGNO_TDATA1, 0); riscv_set_register(target, GDB_REGNO_TDATA1, 0);
break; break;
case 2: case CSR_TDATA1_TYPE_MCONTROL:
if (tdata1 & CSR_MCONTROL_DMODE(riscv_xlen(target))) if (tdata1 & CSR_MCONTROL_DMODE(riscv_xlen(target)))
riscv_set_register(target, GDB_REGNO_TDATA1, 0); riscv_set_register(target, GDB_REGNO_TDATA1, 0);
break; break;
case 6: case CSR_TDATA1_TYPE_MCONTROL6:
if (tdata1 & CSR_MCONTROL6_DMODE(riscv_xlen(target))) if (tdata1 & CSR_MCONTROL6_DMODE(riscv_xlen(target)))
riscv_set_register(target, GDB_REGNO_TDATA1, 0); riscv_set_register(target, GDB_REGNO_TDATA1, 0);
break; break;