From 224e7b4f16784d7872ca42125a66d6266d237668 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Tue, 27 Mar 2018 11:42:32 -0700 Subject: [PATCH] Once more... Less sloppy this time. Change-Id: I4a24e777af3a0d8e072bc1bce0b314738393aa86 --- src/target/riscv/riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 89c0dc7e0..8c18ff7e7 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -2329,7 +2329,7 @@ int riscv_init_registers(struct target *target) * U-mode but without U-mode trap support, the medeleg and * mideleg registers should not exist." */ r->exist = riscv_supports_extension(target, 'S') || - !riscv_supports_extension(target, 'N'); + riscv_supports_extension(target, 'N'); break; }