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Merge pull request #885 from erhankur/fix_tool_warnings 

Fix Checkpatch and Sparse tool warnings
This commit is contained in:
Tim Newsome 2023-07-21 09:12:55 -07:00 committed by GitHub
parent 1a089d8409 617f62a476
commit 21fd3e1d6c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
7 changed files with 63 additions and 69 deletions
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8
src/server/gdb_server.c
View File

@ -3012,7 +3012,8 @@ static int gdb_query_packet(struct connection *connection,
return ERROR_OK; return ERROR_OK;
} }
static bool gdb_handle_vcont_packet(struct connection *connection, const char *packet, int packet_size) static bool gdb_handle_vcont_packet(struct connection *connection, const char *packet,
__attribute__((unused)) int packet_size)
{ {
struct gdb_connection *gdb_connection = connection->priv; struct gdb_connection *gdb_connection = connection->priv;
struct target *target = get_available_target_from_connection(connection); struct target *target = get_available_target_from_connection(connection);
@ -3031,7 +3032,6 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p
if (parse[0] == ';') { if (parse[0] == ';') {
++parse; ++parse;
--packet_size;
} }
/* simple case, a continue packet */ /* simple case, a continue packet */
@ -3070,14 +3070,11 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p
int current_pc = 1; int current_pc = 1;
int64_t thread_id; int64_t thread_id;
parse++; parse++;
packet_size--;
if (parse[0] == ':') { if (parse[0] == ':') {
char *endp; char *endp;
parse++; parse++;
packet_size--;
thread_id = strtoll(parse, &endp, 16); thread_id = strtoll(parse, &endp, 16);
if (endp) { if (endp) {
packet_size -= endp - parse;
parse = endp; parse = endp;
} }
} else { } else {
@ -3115,7 +3112,6 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p
if (parse[0] == ';') { if (parse[0] == ';') {
++parse; ++parse;
--packet_size;
if (parse[0] == 'c') { if (parse[0] == 'c') {
parse += 1; parse += 1;

2
src/target/arm7_9_common.c
View File

@ -1553,7 +1553,6 @@ static int arm7_9_restore_context(struct target *target)
if (dirty) { if (dirty) {
uint32_t mask = 0x0; uint32_t mask = 0x0;
int num_regs = 0;
uint32_t regs[16]; uint32_t regs[16];
if (mode_change) { if (mode_change) {
@ -1576,7 +1575,6 @@ static int arm7_9_restore_context(struct target *target)
if (reg->dirty) { if (reg->dirty) {
regs[j] = buf_get_u32(reg->value, 0, 32); regs[j] = buf_get_u32(reg->value, 0, 32);
mask |= 1 << j; mask |= 1 << j;
num_regs++;
reg->dirty = false; reg->dirty = false;
reg->valid = true; reg->valid = true;
LOG_DEBUG("writing register %i mode %s " LOG_DEBUG("writing register %i mode %s "

4
src/target/riscv/batch.c
View File

@ -127,7 +127,7 @@ int riscv_batch_run(struct riscv_batch *batch)
return ERROR_OK; return ERROR_OK;
} }
void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned address, uint64_t data, void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned int address, uint64_t data,
bool read_back) bool read_back)
{ {
assert(batch->used_scans < batch->allocated_scans); assert(batch->used_scans < batch->allocated_scans);
@ -194,7 +194,7 @@ void riscv_batch_add_nop(struct riscv_batch *batch)
batch->used_scans++; batch->used_scans++;
} }
void dump_field(int idle, const struct scan_field *field) static void dump_field(int idle, const struct scan_field *field)
{ {
static const char * const op_string[] = {"-", "r", "w", "?"}; static const char * const op_string[] = {"-", "r", "w", "?"};
static const char * const status_string[] = {"+", "?", "F", "b"}; static const char * const status_string[] = {"+", "?", "F", "b"};

2
src/target/riscv/batch.h
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@ -59,7 +59,7 @@ bool riscv_batch_full(struct riscv_batch *batch);
int riscv_batch_run(struct riscv_batch *batch); int riscv_batch_run(struct riscv_batch *batch);
/* Adds a DMI write to this batch. */ /* Adds a DMI write to this batch. */
void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned address, uint64_t data, void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned int address, uint64_t data,
bool read_back); bool read_back);
/* DMI reads must be handled in two parts: the first one schedules a read and /* DMI reads must be handled in two parts: the first one schedules a read and

62
src/target/riscv/riscv-013.c
View File

@ -47,9 +47,9 @@ static int riscv013_step_current_hart(struct target *target);
static int riscv013_on_step(struct target *target); static int riscv013_on_step(struct target *target);
static int riscv013_resume_prep(struct target *target); static int riscv013_resume_prep(struct target *target);
static enum riscv_halt_reason riscv013_halt_reason(struct target *target); static enum riscv_halt_reason riscv013_halt_reason(struct target *target);
static int riscv013_write_debug_buffer(struct target *target, unsigned index, static int riscv013_write_debug_buffer(struct target *target, unsigned int index,
riscv_insn_t d); riscv_insn_t d);
static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned int
index); index);
static int riscv013_invalidate_cached_debug_buffer(struct target *target); static int riscv013_invalidate_cached_debug_buffer(struct target *target);
static int riscv013_execute_debug_buffer(struct target *target); static int riscv013_execute_debug_buffer(struct target *target);
@ -1005,7 +1005,7 @@ static uint32_t abstract_memory_size(unsigned width)
* Creates a memory access abstract command. * Creates a memory access abstract command.
*/ */
static uint32_t access_memory_command(struct target *target, bool virtual, static uint32_t access_memory_command(struct target *target, bool virtual,
unsigned width, bool postincrement, bool is_write) unsigned int width, bool postincrement, bool is_write)
{ {
uint32_t command = set_field(0, AC_ACCESS_MEMORY_CMDTYPE, 2); uint32_t command = set_field(0, AC_ACCESS_MEMORY_CMDTYPE, 2);
command = set_field(command, AC_ACCESS_MEMORY_AAMVIRTUAL, virtual); command = set_field(command, AC_ACCESS_MEMORY_AAMVIRTUAL, virtual);
@ -1855,8 +1855,8 @@ static int examine(struct target *target)
if (!halted) { if (!halted) {
r->prepped = true; r->prepped = true;
if (riscv013_halt_go(target) != ERROR_OK) { if (riscv013_halt_go(target) != ERROR_OK) {
LOG_TARGET_ERROR(target, "Fatal: Hart %d failed to halt during examine()", LOG_TARGET_ERROR(target, "Fatal: Hart %d failed to halt during %s",
info->index); info->index, __func__);
return ERROR_FAIL; return ERROR_FAIL;
} }
target->state = TARGET_HALTED; target->state = TARGET_HALTED;
@ -4104,35 +4104,35 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,
uint32_t sbvalue[4] = { 0 }; uint32_t sbvalue[4] = { 0 };
if (size > 12) { if (size > 12) {
sbvalue[3] = ((uint32_t) p[12]) | sbvalue[3] = ((uint32_t)p[12]) |
(((uint32_t) p[13]) << 8) | (((uint32_t)p[13]) << 8) |
(((uint32_t) p[14]) << 16) | (((uint32_t)p[14]) << 16) |
(((uint32_t) p[15]) << 24); (((uint32_t)p[15]) << 24);
riscv_batch_add_dmi_write(batch, DM_SBDATA3, sbvalue[3], false); riscv_batch_add_dmi_write(batch, DM_SBDATA3, sbvalue[3], false);
} }
if (size > 8) { if (size > 8) {
sbvalue[2] = ((uint32_t) p[8]) | sbvalue[2] = ((uint32_t)p[8]) |
(((uint32_t) p[9]) << 8) | (((uint32_t)p[9]) << 8) |
(((uint32_t) p[10]) << 16) | (((uint32_t)p[10]) << 16) |
(((uint32_t) p[11]) << 24); (((uint32_t)p[11]) << 24);
riscv_batch_add_dmi_write(batch, DM_SBDATA2, sbvalue[2], false); riscv_batch_add_dmi_write(batch, DM_SBDATA2, sbvalue[2], false);
} }
if (size > 4) { if (size > 4) {
sbvalue[1] = ((uint32_t) p[4]) | sbvalue[1] = ((uint32_t)p[4]) |
(((uint32_t) p[5]) << 8) | (((uint32_t)p[5]) << 8) |
(((uint32_t) p[6]) << 16) | (((uint32_t)p[6]) << 16) |
(((uint32_t) p[7]) << 24); (((uint32_t)p[7]) << 24);
riscv_batch_add_dmi_write(batch, DM_SBDATA1, sbvalue[1], false); riscv_batch_add_dmi_write(batch, DM_SBDATA1, sbvalue[1], false);
} }
sbvalue[0] = p[0]; sbvalue[0] = p[0];
if (size > 2) { if (size > 2) {
sbvalue[0] |= ((uint32_t) p[2]) << 16; sbvalue[0] |= ((uint32_t)p[2]) << 16;
sbvalue[0] |= ((uint32_t) p[3]) << 24; sbvalue[0] |= ((uint32_t)p[3]) << 24;
} }
if (size > 1) if (size > 1)
sbvalue[0] |= ((uint32_t) p[1]) << 8; sbvalue[0] |= ((uint32_t)p[1]) << 8;
riscv_batch_add_dmi_write(batch, DM_SBDATA0, sbvalue[0], false); riscv_batch_add_dmi_write(batch, DM_SBDATA0, sbvalue[0], false);
@ -4595,7 +4595,7 @@ static int select_prepped_harts(struct target *target)
struct target *t = entry->target; struct target *t = entry->target;
struct riscv_info *info = riscv_info(t); struct riscv_info *info = riscv_info(t);
riscv013_info_t *info_013 = get_info(t); riscv013_info_t *info_013 = get_info(t);
unsigned index = info_013->index; unsigned int index = info_013->index;
LOG_DEBUG("index=%d, coreid=%d, prepped=%d", index, t->coreid, info->prepped); LOG_DEBUG("index=%d, coreid=%d, prepped=%d", index, t->coreid, info->prepped);
if (info->prepped) { if (info->prepped) {
info_013->selected = true; info_013->selected = true;
@ -4779,11 +4779,11 @@ static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
} }
LOG_ERROR("Unknown DCSR cause field: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE)); LOG_ERROR("Unknown DCSR cause field: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE));
LOG_ERROR(" dcsr=0x%" PRIx32, (uint32_t) dcsr); LOG_ERROR(" dcsr=0x%" PRIx32, (uint32_t)dcsr);
return RISCV_HALT_UNKNOWN; return RISCV_HALT_UNKNOWN;
} }
int riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_insn_t data) static int riscv013_write_debug_buffer(struct target *target, unsigned int index, riscv_insn_t data)
{ {
dm013_info_t *dm = get_dm(target); dm013_info_t *dm = get_dm(target);
if (!dm) if (!dm)
@ -4798,14 +4798,14 @@ int riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_ins
return ERROR_OK; return ERROR_OK;
} }
riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned index) static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned int index)
{ {
uint32_t value; uint32_t value;
dmi_read(target, &value, DM_PROGBUF0 + index); dmi_read(target, &value, DM_PROGBUF0 + index);
return value; return value;
} }
int riscv013_invalidate_cached_debug_buffer(struct target *target) static int riscv013_invalidate_cached_debug_buffer(struct target *target)
{ {
dm013_info_t *dm = get_dm(target); dm013_info_t *dm = get_dm(target);
if (!dm) { if (!dm) {
@ -4819,7 +4819,7 @@ int riscv013_invalidate_cached_debug_buffer(struct target *target)
return ERROR_OK; return ERROR_OK;
} }
int riscv013_execute_debug_buffer(struct target *target) static int riscv013_execute_debug_buffer(struct target *target)
{ {
uint32_t run_program = 0; uint32_t run_program = 0;
run_program = set_field(run_program, AC_ACCESS_REGISTER_AARSIZE, 2); run_program = set_field(run_program, AC_ACCESS_REGISTER_AARSIZE, 2);
@ -4830,7 +4830,7 @@ int riscv013_execute_debug_buffer(struct target *target)
return execute_abstract_command(target, run_program); return execute_abstract_command(target, run_program);
} }
void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d) static void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
{ {
RISCV013_INFO(info); RISCV013_INFO(info);
buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_WRITE); buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_WRITE);
@ -4838,7 +4838,7 @@ void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64
buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a); buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a);
} }
void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a) static void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a)
{ {
RISCV013_INFO(info); RISCV013_INFO(info);
buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_READ); buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_READ);
@ -4846,7 +4846,7 @@ void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a)
buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a); buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a);
} }
void riscv013_fill_dmi_nop_u64(struct target *target, char *buf) static void riscv013_fill_dmi_nop_u64(struct target *target, char *buf)
{ {
RISCV013_INFO(info); RISCV013_INFO(info);
buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_NOP); buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_NOP);
@ -4854,7 +4854,7 @@ void riscv013_fill_dmi_nop_u64(struct target *target, char *buf)
buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0); buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0);
} }
int riscv013_dmi_write_u64_bits(struct target *target) static int riscv013_dmi_write_u64_bits(struct target *target)
{ {
RISCV013_INFO(info); RISCV013_INFO(info);
return info->abits + DTM_DMI_DATA_LENGTH + DTM_DMI_OP_LENGTH; return info->abits + DTM_DMI_DATA_LENGTH + DTM_DMI_OP_LENGTH;
@ -4933,7 +4933,7 @@ static int riscv013_step_or_resume_current_hart(struct target *target,
return ERROR_FAIL; return ERROR_FAIL;
} }
void riscv013_clear_abstract_error(struct target *target) static void riscv013_clear_abstract_error(struct target *target)
{ {
/* Wait for busy to go away. */ /* Wait for busy to go away. */
time_t start = time(NULL); time_t start = time(NULL);

50
src/target/riscv/riscv.c
View File

@ -28,7 +28,7 @@
#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1))) #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))) #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
#define field_value(mask, val) set_field((riscv_reg_t) 0, mask, val) #define field_value(mask, val) set_field((riscv_reg_t)0, mask, val)
/*** JTAG registers. ***/ /*** JTAG registers. ***/
@ -516,9 +516,9 @@ static bool can_use_napot_match(struct trigger *trigger)
{ {
riscv_reg_t addr = trigger->address; riscv_reg_t addr = trigger->address;
riscv_reg_t size = trigger->length; riscv_reg_t size = trigger->length;
bool sizePowerOf2 = (size & (size - 1)) == 0; bool size_power_of_2 = (size & (size - 1)) == 0;
bool addrAligned = (addr & (size - 1)) == 0; bool addr_aligned = (addr & (size - 1)) == 0;
return size > 1 && sizePowerOf2 && addrAligned; return size > 1 && size_power_of_2 && addr_aligned;
} }
/* Find the next free trigger of the given type, without talking to the target. */ /* Find the next free trigger of the given type, without talking to the target. */
@ -531,7 +531,7 @@ static int find_next_free_trigger(struct target *target, int type, bool chained,
unsigned int num_found = 0; unsigned int num_found = 0;
unsigned int num_required = chained ? 2 : 1; unsigned int num_required = chained ? 2 : 1;
for (unsigned i = *idx; i < r->trigger_count; i++) { for (unsigned int i = *idx; i < r->trigger_count; i++) {
if (r->trigger_unique_id[i] == -1) { if (r->trigger_unique_id[i] == -1) {
if (r->trigger_tinfo[i] & (1 << type)) { if (r->trigger_tinfo[i] & (1 << type)) {
num_found++; num_found++;
@ -561,7 +561,7 @@ static int find_first_trigger_by_id(struct target *target, int unique_id)
{ {
RISCV_INFO(r); RISCV_INFO(r);
for (unsigned i = 0; i < r->trigger_count; i++) { for (unsigned int i = 0; i < r->trigger_count; i++) {
if (r->trigger_unique_id[i] == unique_id) if (r->trigger_unique_id[i] == unique_id)
return i; return i;
} }
@ -760,8 +760,8 @@ struct match_triggers_tdata1_fields {
riscv_reg_t tdata1_ignore_mask; riscv_reg_t tdata1_ignore_mask;
}; };
static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t2( static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t2(struct target *target,
struct target *target, struct trigger *trigger) struct trigger *trigger)
{ {
RISCV_INFO(r); RISCV_INFO(r);
@ -796,8 +796,8 @@ static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t2(
return result; return result;
} }
static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t6( static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t6(struct target *target,
struct target *target, struct trigger *trigger) struct trigger *trigger)
{ {
bool misa_s = riscv_supports_extension(target, 'S'); bool misa_s = riscv_supports_extension(target, 'S');
bool misa_u = riscv_supports_extension(target, 'U'); bool misa_u = riscv_supports_extension(target, 'U');
@ -1578,7 +1578,7 @@ int riscv_flush_registers(struct target *target)
/** /**
* Set OpenOCD's generic debug reason from the RISC-V halt reason. * Set OpenOCD's generic debug reason from the RISC-V halt reason.
*/ */
int set_debug_reason(struct target *target, enum riscv_halt_reason halt_reason) static int set_debug_reason(struct target *target, enum riscv_halt_reason halt_reason)
{ {
RISCV_INFO(r); RISCV_INFO(r);
r->trigger_hit = -1; r->trigger_hit = -1;
@ -2684,7 +2684,7 @@ static int riscv_checksum_memory(struct target *target,
buf_set_u64(reg_params[1].value, 0, xlen, count); buf_set_u64(reg_params[1].value, 0, xlen, count);
/* 20 second timeout/megabyte */ /* 20 second timeout/megabyte */
int timeout = 20000 * (1 + (count / (1024 * 1024))); unsigned int timeout = 20000 * (1 + (count / (1024 * 1024)));
retval = target_run_algorithm(target, 0, NULL, 2, reg_params, retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
crc_algorithm->address, crc_algorithm->address,
@ -2913,10 +2913,10 @@ int riscv_openocd_poll(struct target *target)
targets = &single_target_list; targets = &single_target_list;
} }
unsigned should_remain_halted = 0; unsigned int should_remain_halted = 0;
unsigned should_resume = 0; unsigned int should_resume = 0;
unsigned halted = 0; unsigned int halted = 0;
unsigned running = 0; unsigned int running = 0;
struct target_list *entry; struct target_list *entry;
foreach_smp_target(entry, targets) { foreach_smp_target(entry, targets) {
struct target *t = entry->target; struct target *t = entry->target;
@ -3509,9 +3509,9 @@ COMMAND_HANDLER(riscv_dmi_write)
- if debug module was reset, in which case progbuf registers - if debug module was reset, in which case progbuf registers
may not retain their value. may not retain their value.
*/ */
bool progbufTouched = (address >= DM_PROGBUF0 && address <= DM_PROGBUF15); bool progbuf_touched = (address >= DM_PROGBUF0 && address <= DM_PROGBUF15);
bool dmDeactivated = (address == DM_DMCONTROL && (value & DM_DMCONTROL_DMACTIVE) == 0); bool dm_deactivated = (address == DM_DMCONTROL && (value & DM_DMCONTROL_DMACTIVE) == 0);
if (progbufTouched || dmDeactivated) { if (progbuf_touched || dm_deactivated) {
if (r->invalidate_cached_debug_buffer) if (r->invalidate_cached_debug_buffer)
r->invalidate_cached_debug_buffer(target); r->invalidate_cached_debug_buffer(target);
} }
@ -3949,7 +3949,7 @@ COMMAND_HANDLER(handle_memory_sample_command)
if (CMD_ARGC == 0) { if (CMD_ARGC == 0) {
command_print(CMD, "Memory sample configuration for %s:", target_name(target)); command_print(CMD, "Memory sample configuration for %s:", target_name(target));
for (unsigned i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++) { for (unsigned int i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++) {
if (r->sample_config.bucket[i].enabled) { if (r->sample_config.bucket[i].enabled) {
command_print(CMD, "bucket %d; address=0x%" TARGET_PRIxADDR "; size=%d", i, command_print(CMD, "bucket %d; address=0x%" TARGET_PRIxADDR "; size=%d", i,
r->sample_config.bucket[i].address, r->sample_config.bucket[i].address,
@ -3969,7 +3969,7 @@ COMMAND_HANDLER(handle_memory_sample_command)
uint32_t bucket; uint32_t bucket;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], bucket); COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], bucket);
if (bucket > ARRAY_SIZE(r->sample_config.bucket)) { if (bucket > ARRAY_SIZE(r->sample_config.bucket)) {
LOG_ERROR("Max bucket number is %d.", (unsigned) ARRAY_SIZE(r->sample_config.bucket)); LOG_ERROR("Max bucket number is %zu.", ARRAY_SIZE(r->sample_config.bucket));
return ERROR_COMMAND_ARGUMENT_INVALID; return ERROR_COMMAND_ARGUMENT_INVALID;
} }
@ -4036,7 +4036,7 @@ COMMAND_HANDLER(handle_dump_sample_buf_command)
command_print(CMD, "%s", encoded); command_print(CMD, "%s", encoded);
free(encoded); free(encoded);
} else { } else {
unsigned i = 0; unsigned int i = 0;
while (i < r->sample_buf.used) { while (i < r->sample_buf.used) {
uint8_t command = r->sample_buf.buf[i++]; uint8_t command = r->sample_buf.buf[i++];
if (command == RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE) { if (command == RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE) {
@ -4080,7 +4080,7 @@ error:
} }
COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key, COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
unsigned value) unsigned int value)
{ {
char full_key[80]; char full_key[80];
snprintf(full_key, sizeof(full_key), "%s.%s", section, key); snprintf(full_key, sizeof(full_key), "%s.%s", section, key);
@ -4437,7 +4437,7 @@ static const struct command_registration riscv_command_handlers[] = {
COMMAND_REGISTRATION_DONE COMMAND_REGISTRATION_DONE
}; };
static unsigned riscv_xlen_nonconst(struct target *target) static unsigned int riscv_xlen_nonconst(struct target *target)
{ {
return riscv_xlen(target); return riscv_xlen(target);
} }
@ -5981,7 +5981,7 @@ int riscv_init_registers(struct target *target)
} else if (r->exist && !list_empty(&info->hide_csr)) { } else if (r->exist && !list_empty(&info->hide_csr)) {
range_list_t *entry; range_list_t *entry;
list_for_each_entry(entry, &info->hide_csr, list) list_for_each_entry(entry, &info->hide_csr, list)
if ((entry->low <= csr_number) && (csr_number <= entry->high)) { if (entry->low <= csr_number && csr_number <= entry->high) {
LOG_TARGET_DEBUG(target, "Hiding CSR %d (name=%s)", csr_number, r->name); LOG_TARGET_DEBUG(target, "Hiding CSR %d (name=%s)", csr_number, r->name);
r->hidden = true; r->hidden = true;
break; break;

4
src/target/target.c
View File

@ -1948,13 +1948,13 @@ static int target_call_timer_callbacks_check_time(int checktime)
return ERROR_OK; return ERROR_OK;
} }
int target_call_timer_callbacks() int target_call_timer_callbacks(void)
{ {
return target_call_timer_callbacks_check_time(1); return target_call_timer_callbacks_check_time(1);
} }
/* invoke periodic callbacks immediately */ /* invoke periodic callbacks immediately */
int target_call_timer_callbacks_now() int target_call_timer_callbacks_now(void)
{ {
return target_call_timer_callbacks_check_time(0); return target_call_timer_callbacks_check_time(0);
} }