Merge pull request #825 from riscv/hypervisor
target/riscv: Set hypervisor bits.
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commit
21d2787d64
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@ -4547,6 +4547,8 @@ static int riscv013_on_step_or_resume(struct target *target, bool step)
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dcsr = set_field(dcsr, CSR_DCSR_EBREAKM, riscv_ebreakm);
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dcsr = set_field(dcsr, CSR_DCSR_EBREAKS, riscv_ebreaks);
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dcsr = set_field(dcsr, CSR_DCSR_EBREAKU, riscv_ebreaku);
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dcsr = set_field(dcsr, CSR_DCSR_EBREAKVS, riscv_ebreaku);
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dcsr = set_field(dcsr, CSR_DCSR_EBREAKVU, riscv_ebreaku);
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if (riscv_set_register(target, GDB_REGNO_DCSR, dcsr) != ERROR_OK)
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return ERROR_FAIL;
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if (riscv_flush_registers(target) != ERROR_OK)
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@ -736,7 +736,9 @@ static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t2(
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static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t6(
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struct target *target, struct trigger *trigger)
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{
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RISCV_INFO(r);
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bool misa_s = riscv_supports_extension(target, 'S');
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bool misa_u = riscv_supports_extension(target, 'U');
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bool misa_h = riscv_supports_extension(target, 'H');
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struct match_triggers_tdata1_fields result = {
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.common =
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@ -744,8 +746,10 @@ static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t6(
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field_value(CSR_MCONTROL6_DMODE(riscv_xlen(target)), 1) |
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field_value(CSR_MCONTROL6_ACTION, CSR_MCONTROL_ACTION_DEBUG_MODE) |
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field_value(CSR_MCONTROL6_M, 1) |
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field_value(CSR_MCONTROL6_S, !!(r->misa & BIT('S' - 'A'))) |
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field_value(CSR_MCONTROL6_U, !!(r->misa & BIT('U' - 'A'))) |
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field_value(CSR_MCONTROL6_S, misa_s) |
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field_value(CSR_MCONTROL6_U, misa_u) |
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field_value(CSR_MCONTROL6_VS, misa_h && misa_s) |
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field_value(CSR_MCONTROL6_VU, misa_h && misa_u) |
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field_value(CSR_MCONTROL6_EXECUTE, trigger->is_execute) |
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field_value(CSR_MCONTROL6_LOAD, trigger->is_read) |
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field_value(CSR_MCONTROL6_STORE, trigger->is_write),
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