flash/nor/stmqspi: Replace macros with static inline functions
There is no good reason to use macros instead of static inline functions. The current code is hard maintain. For example, it changes variables outside of the macro scope. Also, it is conflicting with the C coding style. Change-Id: I5ac9d2ae076ef73c176d4e32b2e7e0a99fa875ab Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6046 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Marc Schink
Antonio Borneo
parent
8132b77d61
commit
210b7d2d16
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@ -52,14 +52,6 @@
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#undef SPIFLASH_READ
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#undef SPIFLASH_PAGE_PROGRAM
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#define READ_REG(a) \
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({ \
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uint32_t _result; \
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\
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retval = target_read_u32(target, io_base + (a), &_result); \
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(retval == ERROR_OK) ? _result : 0x0; \
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})
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/* saved mode settings */
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#define QSPI_MODE (stmqspi_info->saved_ccr & \
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(0xF0000000U | QSPI_DCYC_MASK | QSPI_4LINE_MODE | QSPI_ALTB_MODE | QSPI_ADDR4))
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@ -156,23 +148,6 @@
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#define OPI_CMD(cmd) ((OPI_MODE ? ((((uint16_t)(cmd)) << 8) | (~(cmd) & 0xFFU)) : (cmd)))
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#define OCTOSPI_CMD(mode, ccr, ir) \
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({ \
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retval = target_write_u32(target, io_base + OCTOSPI_CR, \
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OCTOSPI_MODE | (mode)); \
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if (retval == ERROR_OK) \
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retval = target_write_u32(target, io_base + OCTOSPI_TCR, \
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(stmqspi_info->saved_tcr & ~OCTOSPI_DCYC_MASK) | \
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((OPI_MODE && ((mode) == OCTOSPI_READ_MODE)) ? \
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(OPI_DUMMY << OCTOSPI_DCYC_POS) : 0)); \
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if (retval == ERROR_OK) \
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retval = target_write_u32(target, io_base + OCTOSPI_CCR, ccr); \
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if (retval == ERROR_OK) \
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retval = target_write_u32(target, io_base + OCTOSPI_IR, \
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OPI_CMD(ir)); \
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retval; \
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})
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/* convert uint32_t into 4 uint8_t in little endian byte order */
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static inline uint32_t h_to_le_32(uint32_t val)
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{
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@ -208,6 +183,35 @@ struct stmqspi_flash_bank {
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unsigned int sfdp_dummy2; /* number of dummy bytes for SFDP read for flash2 */
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};
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static inline int octospi_cmd(struct flash_bank *bank, uint32_t mode,
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uint32_t ccr, uint32_t ir)
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{
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struct target *target = bank->target;
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const struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
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const uint32_t io_base = stmqspi_info->io_base;
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int retval = target_write_u32(target, io_base + OCTOSPI_CR,
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OCTOSPI_MODE | mode);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u32(target, io_base + OCTOSPI_TCR,
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(stmqspi_info->saved_tcr & ~OCTOSPI_DCYC_MASK) |
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((OPI_MODE && (mode == OCTOSPI_READ_MODE)) ?
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(OPI_DUMMY << OCTOSPI_DCYC_POS) : 0));
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u32(target, io_base + OCTOSPI_CCR, ccr);
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if (retval != ERROR_OK)
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return retval;
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return target_write_u32(target, io_base + OCTOSPI_IR, OPI_CMD(ir));
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}
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FLASH_BANK_COMMAND_HANDLER(stmqspi_flash_bank_command)
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{
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struct stmqspi_flash_bank *stmqspi_info;
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@ -242,19 +246,19 @@ static int poll_busy(struct flash_bank *bank, int timeout)
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struct target *target = bank->target;
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struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
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uint32_t io_base = stmqspi_info->io_base;
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uint32_t spi_sr;
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int retval;
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long long endtime;
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endtime = timeval_ms() + timeout;
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do {
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spi_sr = READ_REG(SPI_SR);
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if ((spi_sr & BIT(SPI_BUSY)) == 0) {
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if (retval == ERROR_OK) {
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/* Clear transmit finished flag */
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retval = target_write_u32(target, io_base + SPI_FCR, BIT(SPI_TCF));
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}
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uint32_t spi_sr;
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int retval = target_read_u32(target, io_base + SPI_SR, &spi_sr);
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if (retval != ERROR_OK)
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return retval;
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if ((spi_sr & BIT(SPI_BUSY)) == 0) {
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/* Clear transmit finished flag */
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return target_write_u32(target, io_base + SPI_FCR, BIT(SPI_TCF));
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} else
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LOG_DEBUG("busy: 0x%08X", spi_sr);
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alive_sleep(1);
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@ -264,6 +268,21 @@ static int poll_busy(struct flash_bank *bank, int timeout)
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return ERROR_FLASH_OPERATION_FAILED;
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}
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static int stmqspi_abort(struct flash_bank *bank)
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{
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struct target *target = bank->target;
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const struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
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const uint32_t io_base = stmqspi_info->io_base;
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uint32_t cr;
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int retval = target_read_u32(target, io_base + SPI_CR, &cr);
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if (retval != ERROR_OK)
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cr = 0;
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return target_write_u32(target, io_base + SPI_CR, cr | BIT(SPI_ABORT));
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}
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/* Set to memory-mapped mode, e.g. after an error */
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static int set_mm_mode(struct flash_bank *bank)
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{
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@ -278,8 +297,7 @@ static int set_mm_mode(struct flash_bank *bank)
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return retval;
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/* Abort any previous operation */
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retval = target_write_u32(target, io_base + SPI_CR,
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READ_REG(SPI_CR) | BIT(SPI_ABORT));
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retval = stmqspi_abort(bank);
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if (retval != ERROR_OK)
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return retval;
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@ -321,8 +339,7 @@ static int read_status_reg(struct flash_bank *bank, uint16_t *status)
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int count, retval;
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/* Abort any previous operation */
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retval = target_write_u32(target, io_base + SPI_CR,
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READ_REG(SPI_CR) | BIT(SPI_ABORT));
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retval = stmqspi_abort(bank);
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if (retval != ERROR_OK)
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return retval;
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@ -340,7 +357,8 @@ static int read_status_reg(struct flash_bank *bank, uint16_t *status)
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/* Read status */
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if (IS_OCTOSPI) {
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retval = OCTOSPI_CMD(OCTOSPI_READ_MODE, OCTOSPI_CCR_READ_STATUS, SPIFLASH_READ_STATUS);
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retval = octospi_cmd(bank, OCTOSPI_READ_MODE, OCTOSPI_CCR_READ_STATUS,
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SPIFLASH_READ_STATUS);
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if (OPI_MODE) {
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/* Dummy address 0, only required for 8-line mode */
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retval = target_write_u32(target, io_base + SPI_AR, 0);
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@ -355,7 +373,8 @@ static int read_status_reg(struct flash_bank *bank, uint16_t *status)
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*status = 0;
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/* for debugging only */
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(void)READ_REG(SPI_SR);
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uint32_t dummy;
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(void)target_read_u32(target, io_base + SPI_SR, &dummy);
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for ( ; count > 0; --count) {
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if ((stmqspi_info->saved_cr & (BIT(SPI_DUAL_FLASH) | BIT(SPI_FSEL_FLASH)))
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@ -416,8 +435,7 @@ static int qspi_write_enable(struct flash_bank *bank)
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int retval;
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/* Abort any previous operation */
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retval = target_write_u32(target, io_base + SPI_CR,
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READ_REG(SPI_CR) | BIT(SPI_ABORT));
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retval = stmqspi_abort(bank);
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if (retval != ERROR_OK)
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return retval;
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@ -428,7 +446,8 @@ static int qspi_write_enable(struct flash_bank *bank)
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/* Send write enable command */
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if (IS_OCTOSPI) {
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retval = OCTOSPI_CMD(OCTOSPI_WRITE_MODE, OCTOSPI_CCR_WRITE_ENABLE, SPIFLASH_WRITE_ENABLE);
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retval = octospi_cmd(bank, OCTOSPI_WRITE_MODE, OCTOSPI_CCR_WRITE_ENABLE,
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SPIFLASH_WRITE_ENABLE);
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if (OPI_MODE) {
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/* Dummy address 0, only required for 8-line mode */
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retval = target_write_u32(target, io_base + SPI_AR, 0);
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@ -527,7 +546,7 @@ COMMAND_HANDLER(stmqspi_handle_mass_erase_command)
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/* Send Mass Erase command */
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if (IS_OCTOSPI)
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retval = OCTOSPI_CMD(OCTOSPI_WRITE_MODE, OCTOSPI_CCR_MASS_ERASE,
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retval = octospi_cmd(bank, OCTOSPI_WRITE_MODE, OCTOSPI_CCR_MASS_ERASE,
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stmqspi_info->dev.chip_erase_cmd);
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else
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retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_MASS_ERASE);
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@ -714,10 +733,15 @@ COMMAND_HANDLER(stmqspi_handle_set)
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bank->size = stmqspi_info->dev.size_in_bytes << dual;
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io_base = stmqspi_info->io_base;
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fsize = (READ_REG(SPI_DCR) >> SPI_FSIZE_POS) & (BIT(SPI_FSIZE_LEN) - 1);
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uint32_t dcr;
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retval = target_read_u32(target, io_base + SPI_DCR, &dcr);
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if (retval != ERROR_OK)
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return retval;
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fsize = (dcr >> SPI_FSIZE_POS) & (BIT(SPI_FSIZE_LEN) - 1);
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LOG_DEBUG("FSIZE = 0x%04x", fsize);
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if (bank->size == BIT(fsize + 1))
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LOG_DEBUG("FSIZE in DCR(1) matches actual capacity. Beware of silicon bug in H7, L4+, MP1.");
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@ -823,8 +847,7 @@ COMMAND_HANDLER(stmqspi_handle_cmd)
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}
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/* Abort any previous operation */
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retval = target_write_u32(target, io_base + SPI_CR,
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READ_REG(SPI_CR) | BIT(SPI_ABORT));
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retval = stmqspi_abort(bank);
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if (retval != ERROR_OK)
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return retval;
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@ -842,7 +865,7 @@ COMMAND_HANDLER(stmqspi_handle_cmd)
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goto err;
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if (IS_OCTOSPI)
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retval = OCTOSPI_CMD(OCTOSPI_WRITE_MODE,
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retval = octospi_cmd(bank, OCTOSPI_WRITE_MODE,
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(OCTOSPI_MODE_CCR & OCTOSPI_NO_ALTB & OCTOSPI_NO_ADDR &
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((num_write == 1) ? OCTOSPI_NO_DATA : ~0U)), cmd_byte);
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else
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@ -879,7 +902,7 @@ COMMAND_HANDLER(stmqspi_handle_cmd)
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if (retval != ERROR_OK)
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goto err;
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if (IS_OCTOSPI)
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retval = OCTOSPI_CMD(OCTOSPI_READ_MODE,
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retval = octospi_cmd(bank, OCTOSPI_READ_MODE,
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(OCTOSPI_MODE_CCR & OCTOSPI_NO_DDTR & OCTOSPI_NO_ALTB & ~OCTOSPI_ADDR4 &
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((num_write == 1) ? OCTOSPI_NO_ADDR : ~0U)) |
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(((num_write - 2) & 0x3U) << SPI_ADSIZE_POS), cmd_byte);
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@ -930,7 +953,7 @@ static int qspi_erase_sector(struct flash_bank *bank, unsigned int sector)
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/* Send Sector Erase command */
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if (IS_OCTOSPI)
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retval = OCTOSPI_CMD(OCTOSPI_WRITE_MODE, OCTOSPI_CCR_SECTOR_ERASE,
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retval = octospi_cmd(bank, OCTOSPI_WRITE_MODE, OCTOSPI_CCR_SECTOR_ERASE,
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stmqspi_info->dev.erase_cmd);
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else
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retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_SECTOR_ERASE);
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@ -1059,7 +1082,6 @@ static int stmqspi_blank_check(struct flash_bank *bank)
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{
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struct target *target = bank->target;
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struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
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uint32_t io_base = stmqspi_info->io_base;
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struct duration bench;
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struct reg_param reg_params[2];
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struct armv7m_algorithm armv7m_info;
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@ -1082,8 +1104,7 @@ static int stmqspi_blank_check(struct flash_bank *bank)
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}
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/* Abort any previous operation */
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retval = target_write_u32(target, io_base + SPI_CR,
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READ_REG(SPI_CR) | BIT(SPI_ABORT));
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retval = stmqspi_abort(bank);
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if (retval != ERROR_OK)
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return retval;
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@ -1568,7 +1589,6 @@ static int stmqspi_read(struct flash_bank *bank, uint8_t *buffer,
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{
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struct target *target = bank->target;
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struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
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uint32_t io_base = stmqspi_info->io_base;
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int retval;
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LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
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@ -1590,8 +1610,7 @@ static int stmqspi_read(struct flash_bank *bank, uint8_t *buffer,
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}
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/* Abort any previous operation */
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retval = target_write_u32(target, io_base + SPI_CR,
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READ_REG(SPI_CR) | BIT(SPI_ABORT));
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retval = stmqspi_abort(bank);
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if (retval != ERROR_OK)
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return retval;
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@ -1608,7 +1627,6 @@ static int stmqspi_write(struct flash_bank *bank, const uint8_t *buffer,
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{
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struct target *target = bank->target;
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struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
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uint32_t io_base = stmqspi_info->io_base;
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unsigned int dual, sector;
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bool octal_dtr;
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int retval;
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@ -1653,8 +1671,7 @@ static int stmqspi_write(struct flash_bank *bank, const uint8_t *buffer,
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}
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/* Abort any previous operation */
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retval = target_write_u32(target, io_base + SPI_CR,
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READ_REG(SPI_CR) | BIT(SPI_ABORT));
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retval = stmqspi_abort(bank);
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if (retval != ERROR_OK)
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return retval;
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@ -1671,7 +1688,6 @@ static int stmqspi_verify(struct flash_bank *bank, const uint8_t *buffer,
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{
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struct target *target = bank->target;
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struct stmqspi_flash_bank *stmqspi_info = bank->driver_priv;
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uint32_t io_base = stmqspi_info->io_base;
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unsigned int dual;
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bool octal_dtr;
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int retval;
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@ -1704,8 +1720,7 @@ static int stmqspi_verify(struct flash_bank *bank, const uint8_t *buffer,
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}
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/* Abort any previous operation */
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retval = target_write_u32(target, io_base + SPI_CR,
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READ_REG(SPI_CR) | BIT(SPI_ABORT));
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retval = stmqspi_abort(bank);
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if (retval != ERROR_OK)
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return retval;
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@ -1757,8 +1772,8 @@ static int find_sfdp_dummy(struct flash_bank *bank, int len)
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/* Read SFDP block */
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if (IS_OCTOSPI)
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retval = OCTOSPI_CMD(OCTOSPI_READ_MODE, OCTOSPI_CCR_READ_SFDP(len),
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SPIFLASH_READ_SFDP);
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retval = octospi_cmd(bank, OCTOSPI_READ_MODE,
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OCTOSPI_CCR_READ_SFDP(len), SPIFLASH_READ_SFDP);
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else
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retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_READ_SFDP);
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if (retval != ERROR_OK)
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@ -1804,8 +1819,7 @@ static int find_sfdp_dummy(struct flash_bank *bank, int len)
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err:
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/* Abort operation */
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retval = target_write_u32(target, io_base + SPI_CR,
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READ_REG(SPI_CR) | BIT(SPI_ABORT));
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retval = stmqspi_abort(bank);
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return retval;
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}
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@ -1880,8 +1894,8 @@ static int read_sfdp_block(struct flash_bank *bank, uint32_t addr,
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/* Read SFDP block */
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if (IS_OCTOSPI)
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retval = OCTOSPI_CMD(OCTOSPI_READ_MODE, OCTOSPI_CCR_READ_SFDP(len),
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SPIFLASH_READ_SFDP);
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retval = octospi_cmd(bank, OCTOSPI_READ_MODE,
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OCTOSPI_CCR_READ_SFDP(len), SPIFLASH_READ_SFDP);
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else
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retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_READ_SFDP);
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if (retval != ERROR_OK)
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@ -1959,8 +1973,7 @@ static int read_flash_id(struct flash_bank *bank, uint32_t *id1, uint32_t *id2)
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/* SPIFLASH_READ_MID causes device in octal mode to go berserk, so don't use in this case */
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for (type = (IS_OCTOSPI && OPI_MODE) ? 1 : 0; type < 2 ; type++) {
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/* Abort any previous operation */
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retval = target_write_u32(target, io_base + SPI_CR,
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READ_REG(SPI_CR) | BIT(SPI_ABORT));
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retval = stmqspi_abort(bank);
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if (retval != ERROR_OK)
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goto err;
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@ -1986,14 +1999,16 @@ static int read_flash_id(struct flash_bank *bank, uint32_t *id1, uint32_t *id2)
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switch (type) {
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case 0:
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if (IS_OCTOSPI)
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retval = OCTOSPI_CMD(OCTOSPI_READ_MODE, OCTOSPI_CCR_READ_MID, SPIFLASH_READ_MID);
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retval = octospi_cmd(bank, OCTOSPI_READ_MODE,
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OCTOSPI_CCR_READ_MID, SPIFLASH_READ_MID);
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else
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retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_READ_MID);
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break;
|
||||
|
||||
case 1:
|
||||
if (IS_OCTOSPI)
|
||||
retval = OCTOSPI_CMD(OCTOSPI_READ_MODE, OCTOSPI_CCR_READ_ID, SPIFLASH_READ_ID);
|
||||
retval = octospi_cmd(bank, OCTOSPI_READ_MODE,
|
||||
OCTOSPI_CCR_READ_ID, SPIFLASH_READ_ID);
|
||||
else
|
||||
retval = target_write_u32(target, io_base + QSPI_CCR, QSPI_CCR_READ_ID);
|
||||
break;
|
||||
|
|
@ -2013,7 +2028,8 @@ static int read_flash_id(struct flash_bank *bank, uint32_t *id1, uint32_t *id2)
|
|||
}
|
||||
|
||||
/* for debugging only */
|
||||
(void)READ_REG(SPI_SR);
|
||||
uint32_t dummy;
|
||||
(void)target_read_u32(target, io_base + SPI_SR, &dummy);
|
||||
|
||||
/* Read ID from Data Register */
|
||||
for (len1 = 0, len2 = 0; count > 0; --count) {
|
||||
|
|
@ -2092,8 +2108,7 @@ static int stmqspi_probe(struct flash_bank *bank)
|
|||
}
|
||||
|
||||
/* Abort any previous operation */
|
||||
retval = target_write_u32(target, io_base + SPI_CR,
|
||||
READ_REG(SPI_CR) | BIT(SPI_ABORT));
|
||||
retval = stmqspi_abort(bank);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
|
|
@ -2112,7 +2127,12 @@ static int stmqspi_probe(struct flash_bank *bank)
|
|||
if (data == magic) {
|
||||
LOG_DEBUG("QSPI_ABR register present");
|
||||
stmqspi_info->octo = false;
|
||||
} else if (READ_REG(OCTOSPI_MAGIC) == OCTO_MAGIC_ID) {
|
||||
} else {
|
||||
uint32_t magic_id;
|
||||
|
||||
retval = target_read_u32(target, io_base + OCTOSPI_MAGIC, &magic_id);
|
||||
|
||||
if (retval == ERROR_OK && magic_id == OCTO_MAGIC_ID) {
|
||||
LOG_DEBUG("OCTOSPI_MAGIC present");
|
||||
stmqspi_info->octo = true;
|
||||
} else {
|
||||
|
|
@ -2121,34 +2141,45 @@ static int stmqspi_probe(struct flash_bank *bank)
|
|||
stmqspi_info->dev.name = "none";
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
/* save current FSEL and DFM bits in QSPI/OCTOSPI_CR, current QSPI/OCTOSPI_CCR value */
|
||||
stmqspi_info->saved_cr = READ_REG(SPI_CR);
|
||||
retval = target_read_u32(target, io_base + SPI_CR, &stmqspi_info->saved_cr);
|
||||
if (retval == ERROR_OK)
|
||||
stmqspi_info->saved_ccr = READ_REG(SPI_CCR);
|
||||
retval = target_read_u32(target, io_base + SPI_CCR, &stmqspi_info->saved_ccr);
|
||||
|
||||
if (IS_OCTOSPI) {
|
||||
uint32_t mtyp;
|
||||
uint32_t dcr1;
|
||||
|
||||
retval = target_read_u32(target, io_base + OCTOSPI_DCR1, &dcr1);
|
||||
|
||||
mtyp = ((READ_REG(OCTOSPI_DCR1) & OCTOSPI_MTYP_MASK)) >> OCTOSPI_MTYP_POS;
|
||||
if (retval == ERROR_OK)
|
||||
stmqspi_info->saved_tcr = READ_REG(OCTOSPI_TCR);
|
||||
retval = target_read_u32(target, io_base + OCTOSPI_TCR,
|
||||
&stmqspi_info->saved_tcr);
|
||||
|
||||
if (retval == ERROR_OK)
|
||||
stmqspi_info->saved_ir = READ_REG(OCTOSPI_IR);
|
||||
if ((mtyp != 0x0) && (mtyp != 0x1)) {
|
||||
retval = ERROR_FAIL;
|
||||
LOG_ERROR("Only regular SPI protocol supported in OCTOSPI");
|
||||
}
|
||||
if (retval == ERROR_OK) {
|
||||
LOG_DEBUG("OCTOSPI at 0x%08" PRIx64 ", io_base at 0x%08" PRIx32 ", OCTOSPI_CR 0x%08"
|
||||
PRIx32 ", OCTOSPI_CCR 0x%08" PRIx32 ", %d-byte addr", bank->base, io_base,
|
||||
stmqspi_info->saved_cr, stmqspi_info->saved_ccr, SPI_ADSIZE);
|
||||
} else {
|
||||
retval = target_read_u32(target, io_base + OCTOSPI_IR,
|
||||
&stmqspi_info->saved_ir);
|
||||
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("No OCTOSPI at io_base 0x%08" PRIx32, io_base);
|
||||
stmqspi_info->probed = false;
|
||||
stmqspi_info->dev.name = "none";
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
const uint32_t mtyp = (dcr1 & OCTOSPI_MTYP_MASK) >> OCTOSPI_MTYP_POS;
|
||||
|
||||
if ((mtyp != 0x0) && (mtyp != 0x1)) {
|
||||
LOG_ERROR("Only regular SPI protocol supported in OCTOSPI");
|
||||
stmqspi_info->probed = false;
|
||||
stmqspi_info->dev.name = "none";
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
LOG_DEBUG("OCTOSPI at 0x%08" PRIx64 ", io_base at 0x%08" PRIx32 ", OCTOSPI_CR 0x%08"
|
||||
PRIx32 ", OCTOSPI_CCR 0x%08" PRIx32 ", %d-byte addr", bank->base, io_base,
|
||||
stmqspi_info->saved_cr, stmqspi_info->saved_ccr, SPI_ADSIZE);
|
||||
} else {
|
||||
if (retval == ERROR_OK) {
|
||||
LOG_DEBUG("QSPI at 0x%08" PRIx64 ", io_base at 0x%08" PRIx32 ", QSPI_CR 0x%08"
|
||||
|
|
@ -2301,10 +2332,14 @@ static int stmqspi_probe(struct flash_bank *bank)
|
|||
/* Set correct size value */
|
||||
bank->size = stmqspi_info->dev.size_in_bytes << dual;
|
||||
|
||||
fsize = ((READ_REG(SPI_DCR) >> SPI_FSIZE_POS) & (BIT(SPI_FSIZE_LEN) - 1));
|
||||
uint32_t dcr;
|
||||
retval = target_read_u32(target, io_base + SPI_DCR, &dcr);
|
||||
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
|
||||
fsize = (dcr >> SPI_FSIZE_POS) & (BIT(SPI_FSIZE_LEN) - 1);
|
||||
|
||||
LOG_DEBUG("FSIZE = 0x%04x", fsize);
|
||||
if (bank->size == BIT((fsize + 1)))
|
||||
LOG_DEBUG("FSIZE in DCR(1) matches actual capacity. Beware of silicon bug in H7, L4+, MP1.");
|
||||
|
|
|
|||
Loading…
Reference in New Issue