diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg
index dc310da44..98f3eea37 100755
--- a/tcl/target/stm32f7x.cfg
+++ b/tcl/target/stm32f7x.cfg
@@ -82,3 +82,27 @@ $_TARGETNAME configure -event trace-config {
 	# assignment
 	mmw 0xE0042004 0x00000020 0
 }
+
+$_TARGETNAME configure -event reset-init {
+	# Configure PLL to boost clock to HSI x 10 (160 MHz)
+	mww 0x40023804 0x08002808   ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P)
+	mww 0x40023C00 0x00000107   ;# FLASH_ACR = PRFTBE | 7(Latency)
+	mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
+	sleep 10                    ;# Wait for PLL to lock
+	mww 0x40023808 0x00009400   ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2)
+	mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
+
+	# Boost SWD frequency
+	# Do not boost JTAG frequency and slow down JTAG memory access or flash write algo
+	# suffers from DAP WAITs
+	if {[using_jtag]} {
+		[[target current] cget -dap] memaccess 16
+	} {
+		adapter_khz 8000
+	}
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reduce speed since CPU speed will slow down to 16MHz with the reset
+	adapter_khz 2000
+}